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Sun, 07 Jul 2024 12:11:39 -0700 (PDT) From: Ajeet Singh X-Google-Original-From: Ajeet Singh To: qemu-devel@nongnu.org Cc: Warner Losh , Stacey Son , Ajeet Singh , Kyle Evans , Sean Bruno , Jessica Clarke , Richard Henderson Subject: [PATCH v2 1/8] bsd-user:Add CPU initialization and management functions Date: Mon, 8 Jul 2024 00:41:21 +0530 Message-Id: <20240707191128.10509-2-itachis@FreeBSD.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240707191128.10509-1-itachis@FreeBSD.org> References: <20240707191128.10509-1-itachis@FreeBSD.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=itachis6234@gmail.com; helo=mail-pf1-x42d.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1720379580105100001 Content-Type: text/plain; charset="utf-8" From: Stacey Son Added function to initialize ARM CPU and check if it supports 64-bit mode. Implemented CPU loop function to handle exceptions and emulate execution of= instructions. Added function to clone CPU state to create a new thread. Included AArch64 specific CPU functions for bsd-user to set and receive thr= ead-local-storage value from the tpidr_el0 register. Introduced structure for storing CPU register states for BSD-USER. Signed-off-by: Stacey Son Signed-off-by: Ajeet Singh Co-authored-by: Kyle Evans Co-authored-by: Sean Bruno Co-authored-by: Jessica Clarke Reviewed-by: Warner Losh Reviewed-by: Richard Henderson --- bsd-user/aarch64/target_arch_cpu.c | 31 +++++ bsd-user/aarch64/target_arch_cpu.h | 191 +++++++++++++++++++++++++++++ bsd-user/aarch64/target_syscall.h | 51 ++++++++ 3 files changed, 273 insertions(+) create mode 100644 bsd-user/aarch64/target_arch_cpu.c create mode 100644 bsd-user/aarch64/target_arch_cpu.h create mode 100644 bsd-user/aarch64/target_syscall.h diff --git a/bsd-user/aarch64/target_arch_cpu.c b/bsd-user/aarch64/target_a= rch_cpu.c new file mode 100644 index 0000000000..b2fa59efaf --- /dev/null +++ b/bsd-user/aarch64/target_arch_cpu.c @@ -0,0 +1,31 @@ +/* + * ARM AArch64 specific CPU for bsd-user + * + * Copyright (c) 2015 Stacey Son + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ +#include "qemu/osdep.h" +#include "target_arch.h" + +/* See cpu_set_user_tls() in arm64/arm64/vm_machdep.c */ +void target_cpu_set_tls(CPUARMState *env, target_ulong newtls) +{ + env->cp15.tpidr_el[0] =3D newtls; +} + +target_ulong target_cpu_get_tls(CPUARMState *env) +{ + return env->cp15.tpidr_el[0]; +} diff --git a/bsd-user/aarch64/target_arch_cpu.h b/bsd-user/aarch64/target_a= rch_cpu.h new file mode 100644 index 0000000000..4e950305d3 --- /dev/null +++ b/bsd-user/aarch64/target_arch_cpu.h @@ -0,0 +1,191 @@ +/* + * ARM AArch64 cpu init and loop + * + * Copyright (c) 2015 Stacey Son + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#ifndef TARGET_ARCH_CPU_H +#define TARGET_ARCH_CPU_H + +#include "target_arch.h" +#include "target/arm/syndrome.h" + +#define TARGET_DEFAULT_CPU_MODEL "any" + +static inline void target_cpu_init(CPUARMState *env, + struct target_pt_regs *regs) +{ + int i; + + if (!(arm_feature(env, ARM_FEATURE_AARCH64))) { + fprintf(stderr, "The selected ARM CPU does not support 64 bit mode= \n"); + exit(1); + } + for (i =3D 0; i < 31; i++) { + env->xregs[i] =3D regs->regs[i]; + } + env->pc =3D regs->pc; + env->xregs[31] =3D regs->sp; +} + + +static inline void target_cpu_loop(CPUARMState *env) +{ + CPUState *cs =3D env_cpu(env); + int trapnr, ec, fsc, si_code, si_signo; + uint64_t code, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8; + uint32_t pstate; + abi_long ret; + + for (;;) { + cpu_exec_start(cs); + trapnr =3D cpu_exec(cs); + cpu_exec_end(cs); + process_queued_cpu_work(cs); + + switch (trapnr) { + case EXCP_SWI: + /* See arm64/arm64/trap.c cpu_fetch_syscall_args() */ + code =3D env->xregs[8]; + if (code =3D=3D TARGET_FREEBSD_NR_syscall || + code =3D=3D TARGET_FREEBSD_NR___syscall) { + code =3D env->xregs[0]; + arg1 =3D env->xregs[1]; + arg2 =3D env->xregs[2]; + arg3 =3D env->xregs[3]; + arg4 =3D env->xregs[4]; + arg5 =3D env->xregs[5]; + arg6 =3D env->xregs[6]; + arg7 =3D env->xregs[7]; + arg8 =3D 0; + } else { + arg1 =3D env->xregs[0]; + arg2 =3D env->xregs[1]; + arg3 =3D env->xregs[2]; + arg4 =3D env->xregs[3]; + arg5 =3D env->xregs[4]; + arg6 =3D env->xregs[5]; + arg7 =3D env->xregs[6]; + arg8 =3D env->xregs[7]; + } + ret =3D do_freebsd_syscall(env, code, arg1, arg2, arg3, + arg4, arg5, arg6, arg7, arg8); + /* + * The carry bit is cleared for no error; set for error. + * See arm64/arm64/vm_machdep.c cpu_set_syscall_retval() + */ + pstate =3D pstate_read(env); + if (ret >=3D 0) { + pstate &=3D ~PSTATE_C; + env->xregs[0] =3D ret; + } else if (ret =3D=3D -TARGET_ERESTART) { + env->pc -=3D 4; + break; + } else if (ret !=3D -TARGET_EJUSTRETURN) { + pstate |=3D PSTATE_C; + env->xregs[0] =3D -ret; + } + pstate_write(env, pstate); + break; + + case EXCP_INTERRUPT: + /* Just indicate that signals should be handle ASAP. */ + break; + + case EXCP_UDEF: + force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLOPN, env->pc); + break; + + + case EXCP_PREFETCH_ABORT: + case EXCP_DATA_ABORT: + /* We should only arrive here with EC in {DATAABORT, INSNABORT= }. */ + ec =3D syn_get_ec(env->exception.syndrome); + assert(ec =3D=3D EC_DATAABORT || ec =3D=3D EC_INSNABORT); + + /* Both EC have the same format for FSC, or close enough. */ + fsc =3D extract32(env->exception.syndrome, 0, 6); + switch (fsc) { + case 0x04 ... 0x07: /* Translation fault, level {0-3} */ + si_signo =3D TARGET_SIGSEGV; + si_code =3D TARGET_SEGV_MAPERR; + break; + case 0x09 ... 0x0b: /* Access flag fault, level {1-3} */ + case 0x0d ... 0x0f: /* Permission fault, level {1-3} */ + si_signo =3D TARGET_SIGSEGV; + si_code =3D TARGET_SEGV_ACCERR; + break; + case 0x11: /* Synchronous Tag Check Fault */ + si_signo =3D TARGET_SIGSEGV; + si_code =3D /* TARGET_SEGV_MTESERR; */ TARGET_SEGV_ACCERR; + break; + case 0x21: /* Alignment fault */ + si_signo =3D TARGET_SIGBUS; + si_code =3D TARGET_BUS_ADRALN; + break; + default: + g_assert_not_reached(); + } + force_sig_fault(si_signo, si_code, env->exception.vaddress); + break; + + case EXCP_DEBUG: + case EXCP_BKPT: + force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, env->pc); + break; + + case EXCP_ATOMIC: + cpu_exec_step_atomic(cs); + break; + + case EXCP_YIELD: + /* nothing to do here for user-mode, just resume guest code */ + break; + default: + fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting= \n", + trapnr); + cpu_dump_state(cs, stderr, 0); + abort(); + } /* switch() */ + process_pending_signals(env); + /* + * Exception return on AArch64 always clears the exclusive + * monitor, so any return to running guest code implies this. + * A strex (successful or otherwise) also clears the monitor, so + * we don't need to specialcase EXCP_STREX. + */ + env->exclusive_addr =3D -1; + } /* for (;;) */ +} + + +/* See arm64/arm64/vm_machdep.c cpu_fork() */ +static inline void target_cpu_clone_regs(CPUARMState *env, target_ulong ne= wsp) +{ + if (newsp) { + env->xregs[31] =3D newsp; + } + env->regs[0] =3D 0; + env->regs[1] =3D 0; + pstate_write(env, 0); +} + +static inline void target_cpu_reset(CPUArchState *env) +{ +} + + +#endif /* TARGET_ARCH_CPU_H */ diff --git a/bsd-user/aarch64/target_syscall.h b/bsd-user/aarch64/target_sy= scall.h new file mode 100644 index 0000000000..08ae913c42 --- /dev/null +++ b/bsd-user/aarch64/target_syscall.h @@ -0,0 +1,51 @@ +/* + * ARM AArch64 specific CPU for bsd-user + * + * Copyright (c) 2015 Stacey D. Son + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#ifndef BSD_USER_AARCH64_TARGET_SYSCALL_H +#define BSD_USER_AARCH64_TARGET_SYSCALL_H + +/* + * The aarch64 registers are named: + * + * x0 through x30 - for 64-bit-wide access (same registers) + * Register '31' is one of two registers depending on the instruction cont= ext: + * For instructions dealing with the stack, it is the stack pointer, name= d rsp + * For all other instructions, it is a "zero" register, which returns 0 w= hen + * read and discards data when written - named rzr (xzr, wzr) + * + * Usage during syscall/function call: + * r0-r7 are used for arguments and return values + * For syscalls, the syscall number is in r8 + * r9-r15 are for temporary values (may get trampled) + * r16-r18 are used for intra-procedure-call and platform values (avoid) + * The called routine is expected to preserve r19-r28 + * r29 and r30 are used as the frame register and link register (avoid) + * See the ARM Procedure Call Reference for details. + */ +struct target_pt_regs { + uint64_t regs[31]; + uint64_t sp; + uint64_t pc; + uint64_t pstate; +}; + +#define TARGET_HW_MACHINE "arm64" +#define TARGET_HW_MACHINE_ARCH "aarch64" + +#endif /* BSD_USER_AARCH64_TARGET_SYSCALL_H */ --=20 2.34.1