From nobody Sun Nov 24 19:46:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1720379578; cv=none; d=zohomail.com; s=zohoarc; b=LCDvci+v3c07lbwB1ZmExWveYS2Jx5lxVG7i46FFY26cYFWaskvWxJ/0zb4lpn7IjRu/xRHvYE/EfOc9ABpjCBoCn2519O93WC5m/zTYAD0iOik7Y9TcCKbR6rP771eyeh+HuzhngWFZgVNKsAPHWl2+cPIb/7Q3k3id2UculOY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1720379578; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=iCBCigvlBMlmY53QeNLfiWH5Dizfub67u6tmw1h+Ik8=; b=flxZVPsr5wPa2Odga5qU9ILGGR26GKmLHyqJBJiIrmp4uYQZ0OW+ANExEl3wdVrZ6kBe/OXW3YQuvJV4CtfgNu8kHeV53i4ZBp+6AyoKmrdy7c88UwavGVo8k5NSkCQ400v6Bj5zfHRFnRe7CHv/3p4qRB3bgEoQ/BlK014DvLM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1720379578860436.00880286464053; Sun, 7 Jul 2024 12:12:58 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sQXIW-0000l8-Pf; Sun, 07 Jul 2024 15:11:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sQXIV-0000kY-82 for qemu-devel@nongnu.org; Sun, 07 Jul 2024 15:11:43 -0400 Received: from mail-pf1-x42d.google.com ([2607:f8b0:4864:20::42d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sQXIT-00057t-13 for qemu-devel@nongnu.org; Sun, 07 Jul 2024 15:11:42 -0400 Received: by mail-pf1-x42d.google.com with SMTP id d2e1a72fcca58-70b09cb7776so1441094b3a.1 for ; Sun, 07 Jul 2024 12:11:40 -0700 (PDT) Received: from localhost.localdomain ([106.222.220.84]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1fac11d8a70sm172156725ad.118.2024.07.07.12.11.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Jul 2024 12:11:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1720379499; x=1720984299; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=iCBCigvlBMlmY53QeNLfiWH5Dizfub67u6tmw1h+Ik8=; b=mJ5dat3ElVBm7zU/K5HDV8JgfvQNNzIzXNatz0ngkSdzwTC9UHVL4ZmQOPvRLSGDuB eKXouoD30Dk28Gjn9uyPbsV4k4NfbzBMork0+fJL9CQYRscUi2xpPHgd2bnjYdcwU6Cx Nh3GljjAOzXFbQgEFnr5NRSXGjZU8HBSg9iAmTLZGZY2m7qInLze4/Q2A/lPuZKpbDRi isbOXlVgc2FJD3jQAq8EW/dUAmC2XuYucu6yFHd2c0ioH+1IaY3zPbXVwOCc7RahqHGN 9lA3S9lJBXJnmD8S8UtFLo2+/uyaZRpfdpe5KCwJmWs2GNWgEhTG5nz7lN5f/r9I4b0A NonQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1720379499; x=1720984299; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=iCBCigvlBMlmY53QeNLfiWH5Dizfub67u6tmw1h+Ik8=; b=OzO/XcuJnhixMzcUiOYY1vUbmwYRejkNRvIROEFdJfJ1IpcmCSLOmbIKa+PsKkIRLY 74PBhqXr3ZF7cIz/GwKr7OsLnfs6h9v4bny/DrDIF0RExCF28YA2C/5gCIn1ilQcg5Oh gMWgvxX9InGMixfgqT2cPSEjiV/qk9hDCWKEoBzS2bYqX3zlHn5rYBZFYie/ZQAZG9Ye cG/K34zQLYiWrzlAG5tg70jGx4DnODn2d6UBtApbmaHRr+rRpwQcwP1zR2X3JMItbqeg aLSnelK8npuNeQxl4v1kzELNl8SVJELMfgnxirNUMMKQD9G33rAf9F3GpKxBQcMF6Y6X kaIw== X-Gm-Message-State: AOJu0YyBud7AqZXIZOOjBebtso9SUZPEvhHIDcb73gSlfNsqAD0JGKmD YmgL0HFWD4dNoTUb3JOqMfNMpszM2zQp2+zpyCv/bA4Tz2OotT+fO+YrixNx X-Google-Smtp-Source: AGHT+IGtMjVZ9yuHJHUd+95VYSAHndOwJ7sXf7c/6fTLCYLrhe3FIbFs6WglJck/lwK9T8OD3pK5vQ== X-Received: by 2002:a05:6a20:1596:b0:1bd:2ce9:9e41 with SMTP id adf61e73a8af0-1c0cc8c95dfmr8392389637.46.1720379499106; Sun, 07 Jul 2024 12:11:39 -0700 (PDT) From: Ajeet Singh X-Google-Original-From: Ajeet Singh To: qemu-devel@nongnu.org Cc: Warner Losh , Stacey Son , Ajeet Singh , Kyle Evans , Sean Bruno , Jessica Clarke , Richard Henderson Subject: [PATCH v2 1/8] bsd-user:Add CPU initialization and management functions Date: Mon, 8 Jul 2024 00:41:21 +0530 Message-Id: <20240707191128.10509-2-itachis@FreeBSD.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240707191128.10509-1-itachis@FreeBSD.org> References: <20240707191128.10509-1-itachis@FreeBSD.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=itachis6234@gmail.com; helo=mail-pf1-x42d.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1720379580105100001 Content-Type: text/plain; charset="utf-8" From: Stacey Son Added function to initialize ARM CPU and check if it supports 64-bit mode. Implemented CPU loop function to handle exceptions and emulate execution of= instructions. Added function to clone CPU state to create a new thread. Included AArch64 specific CPU functions for bsd-user to set and receive thr= ead-local-storage value from the tpidr_el0 register. Introduced structure for storing CPU register states for BSD-USER. Signed-off-by: Stacey Son Signed-off-by: Ajeet Singh Co-authored-by: Kyle Evans Co-authored-by: Sean Bruno Co-authored-by: Jessica Clarke Reviewed-by: Warner Losh Reviewed-by: Richard Henderson --- bsd-user/aarch64/target_arch_cpu.c | 31 +++++ bsd-user/aarch64/target_arch_cpu.h | 191 +++++++++++++++++++++++++++++ bsd-user/aarch64/target_syscall.h | 51 ++++++++ 3 files changed, 273 insertions(+) create mode 100644 bsd-user/aarch64/target_arch_cpu.c create mode 100644 bsd-user/aarch64/target_arch_cpu.h create mode 100644 bsd-user/aarch64/target_syscall.h diff --git a/bsd-user/aarch64/target_arch_cpu.c b/bsd-user/aarch64/target_a= rch_cpu.c new file mode 100644 index 0000000000..b2fa59efaf --- /dev/null +++ b/bsd-user/aarch64/target_arch_cpu.c @@ -0,0 +1,31 @@ +/* + * ARM AArch64 specific CPU for bsd-user + * + * Copyright (c) 2015 Stacey Son + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ +#include "qemu/osdep.h" +#include "target_arch.h" + +/* See cpu_set_user_tls() in arm64/arm64/vm_machdep.c */ +void target_cpu_set_tls(CPUARMState *env, target_ulong newtls) +{ + env->cp15.tpidr_el[0] =3D newtls; +} + +target_ulong target_cpu_get_tls(CPUARMState *env) +{ + return env->cp15.tpidr_el[0]; +} diff --git a/bsd-user/aarch64/target_arch_cpu.h b/bsd-user/aarch64/target_a= rch_cpu.h new file mode 100644 index 0000000000..4e950305d3 --- /dev/null +++ b/bsd-user/aarch64/target_arch_cpu.h @@ -0,0 +1,191 @@ +/* + * ARM AArch64 cpu init and loop + * + * Copyright (c) 2015 Stacey Son + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#ifndef TARGET_ARCH_CPU_H +#define TARGET_ARCH_CPU_H + +#include "target_arch.h" +#include "target/arm/syndrome.h" + +#define TARGET_DEFAULT_CPU_MODEL "any" + +static inline void target_cpu_init(CPUARMState *env, + struct target_pt_regs *regs) +{ + int i; + + if (!(arm_feature(env, ARM_FEATURE_AARCH64))) { + fprintf(stderr, "The selected ARM CPU does not support 64 bit mode= \n"); + exit(1); + } + for (i =3D 0; i < 31; i++) { + env->xregs[i] =3D regs->regs[i]; + } + env->pc =3D regs->pc; + env->xregs[31] =3D regs->sp; +} + + +static inline void target_cpu_loop(CPUARMState *env) +{ + CPUState *cs =3D env_cpu(env); + int trapnr, ec, fsc, si_code, si_signo; + uint64_t code, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8; + uint32_t pstate; + abi_long ret; + + for (;;) { + cpu_exec_start(cs); + trapnr =3D cpu_exec(cs); + cpu_exec_end(cs); + process_queued_cpu_work(cs); + + switch (trapnr) { + case EXCP_SWI: + /* See arm64/arm64/trap.c cpu_fetch_syscall_args() */ + code =3D env->xregs[8]; + if (code =3D=3D TARGET_FREEBSD_NR_syscall || + code =3D=3D TARGET_FREEBSD_NR___syscall) { + code =3D env->xregs[0]; + arg1 =3D env->xregs[1]; + arg2 =3D env->xregs[2]; + arg3 =3D env->xregs[3]; + arg4 =3D env->xregs[4]; + arg5 =3D env->xregs[5]; + arg6 =3D env->xregs[6]; + arg7 =3D env->xregs[7]; + arg8 =3D 0; + } else { + arg1 =3D env->xregs[0]; + arg2 =3D env->xregs[1]; + arg3 =3D env->xregs[2]; + arg4 =3D env->xregs[3]; + arg5 =3D env->xregs[4]; + arg6 =3D env->xregs[5]; + arg7 =3D env->xregs[6]; + arg8 =3D env->xregs[7]; + } + ret =3D do_freebsd_syscall(env, code, arg1, arg2, arg3, + arg4, arg5, arg6, arg7, arg8); + /* + * The carry bit is cleared for no error; set for error. + * See arm64/arm64/vm_machdep.c cpu_set_syscall_retval() + */ + pstate =3D pstate_read(env); + if (ret >=3D 0) { + pstate &=3D ~PSTATE_C; + env->xregs[0] =3D ret; + } else if (ret =3D=3D -TARGET_ERESTART) { + env->pc -=3D 4; + break; + } else if (ret !=3D -TARGET_EJUSTRETURN) { + pstate |=3D PSTATE_C; + env->xregs[0] =3D -ret; + } + pstate_write(env, pstate); + break; + + case EXCP_INTERRUPT: + /* Just indicate that signals should be handle ASAP. */ + break; + + case EXCP_UDEF: + force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLOPN, env->pc); + break; + + + case EXCP_PREFETCH_ABORT: + case EXCP_DATA_ABORT: + /* We should only arrive here with EC in {DATAABORT, INSNABORT= }. */ + ec =3D syn_get_ec(env->exception.syndrome); + assert(ec =3D=3D EC_DATAABORT || ec =3D=3D EC_INSNABORT); + + /* Both EC have the same format for FSC, or close enough. */ + fsc =3D extract32(env->exception.syndrome, 0, 6); + switch (fsc) { + case 0x04 ... 0x07: /* Translation fault, level {0-3} */ + si_signo =3D TARGET_SIGSEGV; + si_code =3D TARGET_SEGV_MAPERR; + break; + case 0x09 ... 0x0b: /* Access flag fault, level {1-3} */ + case 0x0d ... 0x0f: /* Permission fault, level {1-3} */ + si_signo =3D TARGET_SIGSEGV; + si_code =3D TARGET_SEGV_ACCERR; + break; + case 0x11: /* Synchronous Tag Check Fault */ + si_signo =3D TARGET_SIGSEGV; + si_code =3D /* TARGET_SEGV_MTESERR; */ TARGET_SEGV_ACCERR; + break; + case 0x21: /* Alignment fault */ + si_signo =3D TARGET_SIGBUS; + si_code =3D TARGET_BUS_ADRALN; + break; + default: + g_assert_not_reached(); + } + force_sig_fault(si_signo, si_code, env->exception.vaddress); + break; + + case EXCP_DEBUG: + case EXCP_BKPT: + force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, env->pc); + break; + + case EXCP_ATOMIC: + cpu_exec_step_atomic(cs); + break; + + case EXCP_YIELD: + /* nothing to do here for user-mode, just resume guest code */ + break; + default: + fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting= \n", + trapnr); + cpu_dump_state(cs, stderr, 0); + abort(); + } /* switch() */ + process_pending_signals(env); + /* + * Exception return on AArch64 always clears the exclusive + * monitor, so any return to running guest code implies this. + * A strex (successful or otherwise) also clears the monitor, so + * we don't need to specialcase EXCP_STREX. + */ + env->exclusive_addr =3D -1; + } /* for (;;) */ +} + + +/* See arm64/arm64/vm_machdep.c cpu_fork() */ +static inline void target_cpu_clone_regs(CPUARMState *env, target_ulong ne= wsp) +{ + if (newsp) { + env->xregs[31] =3D newsp; + } + env->regs[0] =3D 0; + env->regs[1] =3D 0; + pstate_write(env, 0); +} + +static inline void target_cpu_reset(CPUArchState *env) +{ +} + + +#endif /* TARGET_ARCH_CPU_H */ diff --git a/bsd-user/aarch64/target_syscall.h b/bsd-user/aarch64/target_sy= scall.h new file mode 100644 index 0000000000..08ae913c42 --- /dev/null +++ b/bsd-user/aarch64/target_syscall.h @@ -0,0 +1,51 @@ +/* + * ARM AArch64 specific CPU for bsd-user + * + * Copyright (c) 2015 Stacey D. Son + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#ifndef BSD_USER_AARCH64_TARGET_SYSCALL_H +#define BSD_USER_AARCH64_TARGET_SYSCALL_H + +/* + * The aarch64 registers are named: + * + * x0 through x30 - for 64-bit-wide access (same registers) + * Register '31' is one of two registers depending on the instruction cont= ext: + * For instructions dealing with the stack, it is the stack pointer, name= d rsp + * For all other instructions, it is a "zero" register, which returns 0 w= hen + * read and discards data when written - named rzr (xzr, wzr) + * + * Usage during syscall/function call: + * r0-r7 are used for arguments and return values + * For syscalls, the syscall number is in r8 + * r9-r15 are for temporary values (may get trampled) + * r16-r18 are used for intra-procedure-call and platform values (avoid) + * The called routine is expected to preserve r19-r28 + * r29 and r30 are used as the frame register and link register (avoid) + * See the ARM Procedure Call Reference for details. + */ +struct target_pt_regs { + uint64_t regs[31]; + uint64_t sp; + uint64_t pc; + uint64_t pstate; +}; + +#define TARGET_HW_MACHINE "arm64" +#define TARGET_HW_MACHINE_ARCH "aarch64" + +#endif /* BSD_USER_AARCH64_TARGET_SYSCALL_H */ --=20 2.34.1 From nobody Sun Nov 24 19:46:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1720379613; cv=none; d=zohomail.com; s=zohoarc; b=jUpNhg88ZQd2MzaImx2VR/RvEj/vc+cOFsBJ28b2yIeRTyVbIMDeK3bhkz7H4pEABdnjCQz80Wlkmze1PAvnHkL7BaRYamJgpb2CRWmbaAroslXS8VK+7Nv4R44h2M8RtbMtcPypWAQjzKcY+fBbIvqkh8W7h2PP1gK8OAn/9e4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1720379613; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=FbnoTBSKIDJs2zVqo6kHAJTCsCuXr7TaJjTdy5frhH8=; b=nqfWZerUnGkOaHKvmC/tmGknKZ1qSBpPrjC3VOknTgRMStqWcgzjpccDg/4Ij5cObKmigLwcv9A3xMyl5TTd7O7Ef88Zq6MTdROKQkVpQJI9oed+aGDCoKISKqFt1elCOt/wJB62pAME67jGWtm6ozn+LQO1g0ncSeoQJVVsq+c= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1720379613834760.5557500518973; Sun, 7 Jul 2024 12:13:33 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sQXIZ-0000lj-6h; Sun, 07 Jul 2024 15:11:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sQXIX-0000lL-O4 for qemu-devel@nongnu.org; Sun, 07 Jul 2024 15:11:45 -0400 Received: from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sQXIV-000589-CL for qemu-devel@nongnu.org; Sun, 07 Jul 2024 15:11:45 -0400 Received: by mail-pl1-x62a.google.com with SMTP id d9443c01a7336-1fb0d7e4ee9so20861075ad.3 for ; Sun, 07 Jul 2024 12:11:43 -0700 (PDT) Received: from localhost.localdomain ([106.222.220.84]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1fac11d8a70sm172156725ad.118.2024.07.07.12.11.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Jul 2024 12:11:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1720379502; x=1720984302; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=FbnoTBSKIDJs2zVqo6kHAJTCsCuXr7TaJjTdy5frhH8=; b=AHyARD+JlPAK3embU+MPYi5xyaa04mfZgeLgDIuxpN7dRLY5rzJfHd0MbFG+2Adzar wzcvknxCANjkpZTZWJ13vtF/ubeNoNiAzKWn3Hhdk8N9PxA1x/5XLWSapcB2Ck8YIFdu hgAY30qVXL7wvAM29zMnEP4+ZKCUQm/chjyXHDgKIx19Q18jEPv6rwaVdvY6Jr/q437D tqbwKhuz33ueFbDF5GCds40E5ZMrz7ZMr/UcFYqwezCbjIGMXXDPR+I4nC9oDZhyPXnP 1WPeeBC5AKy631XVOu3iuloEUTlu4RfZfV3treEsMvettPrJ+3lvEvu3IoIyElRKuy5X bklQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1720379502; x=1720984302; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FbnoTBSKIDJs2zVqo6kHAJTCsCuXr7TaJjTdy5frhH8=; b=NB8n1811ewtgdggQlObSL45pnDtmDUHXJ4qFFcfHmyeVKwk21vmhNxRsgniRcxxdM3 Z2VWHqTFZIlhfHIG81FvJhMQIHaSxp6q/fk4oqvTn62G7uoxvMP/e4lKp84/Gu7wknhn zLwUoF234ev9zEZ2G++v+Bv+dfNfVc8bWtYw2IO7BrXbNyj0/qhFt0hsjLOw1lkQ0BxX vXbU/gGU5ACgO0CRDRFFpFuZeoBwDfZsAz40FGXAgAtLsZTVzWD1vVIujilahWce1k5T c6zgnjP8XfYjcIMbMS5X1+qiHzjfI9L08pIqjfH1ueW0YBoGou7hoQKFDwB5aWvJJnP8 9gjw== X-Gm-Message-State: AOJu0YyEPwxG4c/DKmRLIPL+jarb/F8XnJ2t5XczInQs0hTgOOM40aZm aTl7XV2xZuoMHqtzrgW1ZNCgLM7vFF57ZakMWa2DcvWUVopWJjGDzKt5YNqy X-Google-Smtp-Source: AGHT+IHDWtNujByHJWSSnbiLcx/hpE2FYpYT2WHNUaEWmYpamxmE1ePywrCCo4RRVW59Os8psFEmJw== X-Received: by 2002:a17:903:41d0:b0:1f9:b16d:f94f with SMTP id d9443c01a7336-1fb33ed08bbmr71434795ad.39.1720379501566; Sun, 07 Jul 2024 12:11:41 -0700 (PDT) From: Ajeet Singh X-Google-Original-From: Ajeet Singh To: qemu-devel@nongnu.org Cc: Warner Losh , Stacey Son , Ajeet Singh , Jessica Clarke , Sean Bruno , Richard Henderson Subject: [PATCH v2 2/8] bsd-user:Add AArch64 register handling and related functions Date: Mon, 8 Jul 2024 00:41:22 +0530 Message-Id: <20240707191128.10509-3-itachis@FreeBSD.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240707191128.10509-1-itachis@FreeBSD.org> References: <20240707191128.10509-1-itachis@FreeBSD.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=itachis6234@gmail.com; helo=mail-pl1-x62a.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1720379614187100001 Content-Type: text/plain; charset="utf-8" From: Stacey Son Added header file for managing CPU register states in FreeBSD user mode. Introduced prototypes for setting and getting thread-local storage (TLS). Implemented AArch64 sysarch() system call emulation and a printing function. Added function for setting up thread upcall to add thread support to BSD-US= ER. Initialized thread's register state during thread setup. Updated ARM AArch64 VM parameter definitions for bsd-user, including addres= s spaces for FreeBSD/arm64 and a function for getting the stack pointer from CPU and setting a return valu= e. Signed-off-by: Stacey Son Signed-off-by: Ajeet Singh Co-authored-by: Jessica Clarke Co-authored-by: Sean Bruno Co-authored-by: Warner Losh Reviewed-by: Richard Henderson --- bsd-user/aarch64/target_arch.h | 28 +++++++++++ bsd-user/aarch64/target_arch_reg.h | 56 +++++++++++++++++++++ bsd-user/aarch64/target_arch_sysarch.h | 42 ++++++++++++++++ bsd-user/aarch64/target_arch_thread.h | 61 +++++++++++++++++++++++ bsd-user/aarch64/target_arch_vmparam.h | 68 ++++++++++++++++++++++++++ 5 files changed, 255 insertions(+) create mode 100644 bsd-user/aarch64/target_arch.h create mode 100644 bsd-user/aarch64/target_arch_reg.h create mode 100644 bsd-user/aarch64/target_arch_sysarch.h create mode 100644 bsd-user/aarch64/target_arch_thread.h create mode 100644 bsd-user/aarch64/target_arch_vmparam.h diff --git a/bsd-user/aarch64/target_arch.h b/bsd-user/aarch64/target_arch.h new file mode 100644 index 0000000000..27f47de8eb --- /dev/null +++ b/bsd-user/aarch64/target_arch.h @@ -0,0 +1,28 @@ +/* + * ARM AArch64 specific prototypes for bsd-user + * + * Copyright (c) 2015 Stacey D. Son + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#ifndef TARGET_ARCH_H +#define TARGET_ARCH_H + +#include "qemu.h" + +void target_cpu_set_tls(CPUARMState *env, target_ulong newtls); +target_ulong target_cpu_get_tls(CPUARMState *env); + +#endif /* TARGET_ARCH_H */ diff --git a/bsd-user/aarch64/target_arch_reg.h b/bsd-user/aarch64/target_a= rch_reg.h new file mode 100644 index 0000000000..5c7154f0c1 --- /dev/null +++ b/bsd-user/aarch64/target_arch_reg.h @@ -0,0 +1,56 @@ +/* + * FreeBSD arm64 register structures + * + * Copyright (c) 2015 Stacey Son + * All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#ifndef TARGET_ARCH_REG_H +#define TARGET_ARCH_REG_H + +/* See sys/arm64/include/reg.h */ +typedef struct target_reg { + uint64_t x[30]; + uint64_t lr; + uint64_t sp; + uint64_t elr; + uint64_t spsr; +} target_reg_t; + +typedef struct target_fpreg { + __uint128_t fp_q[32]; + uint32_t fp_sr; + uint32_t fp_cr; +} target_fpreg_t; + +#define tswapreg(ptr) tswapal(ptr) + +static inline void target_copy_regs(target_reg_t *regs, CPUARMState *env) +{ + int i; + + for (i =3D 0; i < 30; i++) { + regs->x[i] =3D tswapreg(env->xregs[i]); + } + regs->lr =3D tswapreg(env->xregs[30]); + regs->sp =3D tswapreg(env->xregs[31]); + regs->elr =3D tswapreg(env->pc); + regs->spsr =3D tswapreg(pstate_read(env)); +} + +#undef tswapreg + +#endif /* TARGET_ARCH_REG_H */ diff --git a/bsd-user/aarch64/target_arch_sysarch.h b/bsd-user/aarch64/targ= et_arch_sysarch.h new file mode 100644 index 0000000000..b003015daf --- /dev/null +++ b/bsd-user/aarch64/target_arch_sysarch.h @@ -0,0 +1,42 @@ +/* + * ARM AArch64 sysarch() system call emulation for bsd-user. + * + * Copyright (c) 2015 + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#ifndef TARGET_ARCH_SYSARCH_H +#define TARGET_ARCH_SYSARCH_H + +#include "target_syscall.h" +#include "target_arch.h" + +/* See sysarch() in sys/arm64/arm64/sys_machdep.c */ +static inline abi_long do_freebsd_arch_sysarch(CPUARMState *env, int op, + abi_ulong parms) +{ + int ret =3D -TARGET_EOPNOTSUPP; + + fprintf(stderr, "sysarch"); + return ret; +} + +static inline void do_freebsd_arch_print_sysarch( + const struct syscallname *name, abi_long arg1, abi_long arg2, + abi_long arg3, abi_long arg4, abi_long arg5, abi_long arg6) +{ +} + +#endif /* TARGET_ARCH_SYSARCH_H */ diff --git a/bsd-user/aarch64/target_arch_thread.h b/bsd-user/aarch64/targe= t_arch_thread.h new file mode 100644 index 0000000000..4c911e605a --- /dev/null +++ b/bsd-user/aarch64/target_arch_thread.h @@ -0,0 +1,61 @@ +/* + * ARM AArch64 thread support for bsd-user. + * + * Copyright (c) 2015 Stacey D. Son + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#ifndef TARGET_ARCH_THREAD_H +#define TARGET_ARCH_THREAD_H + +/* Compare to arm64/arm64/vm_machdep.c cpu_set_upcall_kse() */ +static inline void target_thread_set_upcall(CPUARMState *regs, abi_ulong e= ntry, + abi_ulong arg, abi_ulong stack_base, abi_ulong stack_size) +{ + abi_ulong sp; + + /* + * Make sure the stack is properly aligned. + * arm64/include/param.h (STACKLIGN() macro) + */ + sp =3D ROUND_DOWN(stack_base + stack_size, 16); + + /* sp =3D stack base */ + regs->xregs[31] =3D sp; + /* pc =3D start function entry */ + regs->pc =3D entry; + /* r0 =3D arg */ + regs->xregs[0] =3D arg; + + =20 +} + +static inline void target_thread_init(struct target_pt_regs *regs, + struct image_info *infop) +{ + abi_long stack =3D infop->start_stack; + + /* + * Make sure the stack is properly aligned. + * arm64/include/param.h (STACKLIGN() macro) + */ + + memset(regs, 0, sizeof(*regs)); + regs->regs[0] =3D infop->start_stack; + regs->pc =3D infop->entry; + regs->sp =3D ROUND_DOWN(stack, 16); +} + +#endif /* TARGET_ARCH_THREAD_H */ diff --git a/bsd-user/aarch64/target_arch_vmparam.h b/bsd-user/aarch64/targ= et_arch_vmparam.h new file mode 100644 index 0000000000..dc66e1289b --- /dev/null +++ b/bsd-user/aarch64/target_arch_vmparam.h @@ -0,0 +1,68 @@ +/* + * ARM AArch64 VM parameters definitions for bsd-user. + * + * Copyright (c) 2015 Stacey D. Son + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#ifndef TARGET_ARCH_VMPARAM_H +#define TARGET_ARCH_VMPARAM_H + +#include "cpu.h" + +/** + * FreeBSD/arm64 Address space layout. + * + * ARMv8 implements up to a 48 bit virtual address space. The address spac= e is + * split into 2 regions at each end of the 64 bit address space, with an + * out of range "hole" in the middle. + * + * We limit the size of the two spaces to 39 bits each. + * + * Upper region: 0xffffffffffffffff + * 0xffffff8000000000 + * + * Hole: 0xffffff7fffffffff + * 0x0000008000000000 + * + * Lower region: 0x0000007fffffffff + * 0x0000000000000000 + * + * The upper region for the kernel, and the lower region for userland. + */ + + +/* compare to sys/arm64/include/vmparam.h */ +#define TARGET_MAXTSIZ (1 * GiB) /* max text size */ +#define TARGET_DFLDSIZ (128 * MiB) /* initial data size limit= */ +#define TARGET_MAXDSIZ (1 * GiB) /* max data size */ +#define TARGET_DFLSSIZ (128 * MiB) /* initial stack size limi= t */ +#define TARGET_MAXSSIZ (1 * GiB) /* max stack size */ +#define TARGET_SGROWSIZ (128 * KiB) /* amount to grow stack */ + + /* KERNBASE - 512 MB */ +#define TARGET_VM_MAXUSER_ADDRESS (0x00007fffff000000ULL - (512 * MiB)) +#define TARGET_USRSTACK TARGET_VM_MAXUSER_ADDRESS + +static inline abi_ulong get_sp_from_cpustate(CPUARMState *state) +{ + return state->xregs[31]; /* sp */ +} + +static inline void set_second_rval(CPUARMState *state, abi_ulong retval2) +{ + state->xregs[1] =3D retval2; /* XXX not really used on 64-bit arch */ +} +#endif /* TARGET_ARCH_VMPARAM_H */ --=20 2.34.1 From nobody Sun Nov 24 19:46:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1720379566; cv=none; d=zohomail.com; s=zohoarc; b=Whro+If222tYGSpj3ZaQrQXwUkJk4yQVqfvIgmvA1OFdfom6QH2nAwfs4op7dH0pyeD3voEOfzVRnRQBxq8gCbcmHyFN0w2JKU2HiMnDvf9MVARdKfdfQRoeFUIBpJxQP7afB2i50Hp5b6coYyy54dE88wcvfwV8pdSbHsgwOow= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1720379566; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=wdfibBhkqHXEKbib4pcHbTKhIdldRjkJogYjN56GcWY=; b=CcJKx55FkonfaurHvE3XX7v1yr9wLRtCaVrths69mk92wznwVMI7CMbutKvdyWi7y+pBaXxthYAaXXAXIruyuZwmYe5IFZ4Bsz2oH7DMjFAvVeTJb6e28Ktz+TKGTnD7q4izgYvMebc8Y9l/pmqdIKMc/2CoJlOj0om/azisZjQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1720379566350706.3889625312759; Sun, 7 Jul 2024 12:12:46 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sQXIb-0000mG-DI; Sun, 07 Jul 2024 15:11:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sQXIZ-0000lk-TM for qemu-devel@nongnu.org; Sun, 07 Jul 2024 15:11:47 -0400 Received: from mail-pf1-x435.google.com ([2607:f8b0:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sQXIX-00058U-Qt for qemu-devel@nongnu.org; Sun, 07 Jul 2024 15:11:47 -0400 Received: by mail-pf1-x435.google.com with SMTP id d2e1a72fcca58-70af4868d3dso1891750b3a.3 for ; Sun, 07 Jul 2024 12:11:45 -0700 (PDT) Received: from localhost.localdomain ([106.222.220.84]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1fac11d8a70sm172156725ad.118.2024.07.07.12.11.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Jul 2024 12:11:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1720379504; x=1720984304; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wdfibBhkqHXEKbib4pcHbTKhIdldRjkJogYjN56GcWY=; b=XAnxL1SvmikR97i30YxhBIrddo5UTAL4g35WfQXRx70ABNTKCFZ9shh589PBLgQqMy tw99VPgcRB/2rT8uXreRsOg+lvl+G7YJa9GrLILw52lPWjdTm2slcx88LmFAl50WxlBt 2iRSBt2R3vsp7ZsbI/GvRceZyzN1NazdSOJxqqLUNLJL8Nh4yFPb5GEpTxS5x6DuSerJ V3ipW1XBGivl9f5pE4GiHNFMzhm3Gy6bmXwWPiOVV94+H+JVJkTpO6XTv5zCiycOUamQ b0cMs0wQhlB0IrUUBlNH2af0nxweUmYKIjdzvj+XGCJ0cDDyVQkTczayWYn945cKDL3W QzVQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1720379504; x=1720984304; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wdfibBhkqHXEKbib4pcHbTKhIdldRjkJogYjN56GcWY=; b=ho/MElxQY3LBh5uQdoTlWGhYLsNOZOSEZOcj4dsszSzP58F0ZaOfVo1EomMpgtnxu3 6mKFERaiswtZmFVPbk56ao9Di1p0cg8WfFR0MhR82jpo1lwPcnWZ5J5AMPbDPxfYLDUl MZOsBfhdTNPR+MqZqFUmwXaEHYTjAsrJlvpdUvWSYJ2XmdAffEExA6ivf2CCGaOWqcsY ZoeZnvcb/0xGXIPQnQfTre5TxuDKwKU/WWGmZlmxwNGzBivQQ8VI1gWARwiT1Rqspzfd humZqalUTDGZpKxpHfCxPRvYXIn269om/sda9WDnMeFgRaqf7ETtYBCJ4no9HAhCuDrB InNA== X-Gm-Message-State: AOJu0YzdwMy3rU2ru72zDQDsDGEL3U3KEEGWx3HbVli0vAw7Yb2LT+OH V75zsjJLIuRTgs4hiakeMKr/oVWxpqoFOvnUwOY7cDCibNHcmXdxWiaLkmxq X-Google-Smtp-Source: AGHT+IG9XO/cmUFWaaJV3EhQYvwN8ccQZWh2EK5qhP5BPrlpkwM322B7DVQ0BluScwS3DwpBea0vqg== X-Received: by 2002:a05:6a20:d49b:b0:1c0:f33e:aae3 with SMTP id adf61e73a8af0-1c0f33eb034mr660380637.59.1720379503855; Sun, 07 Jul 2024 12:11:43 -0700 (PDT) From: Ajeet Singh X-Google-Original-From: Ajeet Singh To: qemu-devel@nongnu.org Cc: Warner Losh , Stacey Son , Ajeet Singh , Kyle Evans , Richard Henderson Subject: [PATCH v2 3/8] bsd-user:Add ARM AArch64 support and capabilities Date: Mon, 8 Jul 2024 00:41:23 +0530 Message-Id: <20240707191128.10509-4-itachis@FreeBSD.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240707191128.10509-1-itachis@FreeBSD.org> References: <20240707191128.10509-1-itachis@FreeBSD.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=itachis6234@gmail.com; helo=mail-pf1-x435.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1720379568003100003 Content-Type: text/plain; charset="utf-8" From: Warner Losh Added function to access rval2 by accessing the x1 register. Defined ARM AArch64 ELF parameters including mmap and dynamic load addresse= s. Introduced extensive hardware capability definitions and macros for retriev= ing hardware capability (hwcap) flags. Implemented function to retrieve ARM AArch64 hardware capabilities using th= e `GET_FEATURE_ID` macro. Added function to retrieve extended ARM AArch64 hardware capability flags. Signed-off-by: Stacey Son Signed-off-by: Ajeet Singh Signed-off-by: Warner Losh Co-authored-by: Kyle Evans Reviewed-by: Richard Henderson --- bsd-user/aarch64/target_arch_elf.h | 165 +++++++++++++++++++++++++ bsd-user/aarch64/target_arch_vmparam.h | 6 + 2 files changed, 171 insertions(+) create mode 100644 bsd-user/aarch64/target_arch_elf.h diff --git a/bsd-user/aarch64/target_arch_elf.h b/bsd-user/aarch64/target_a= rch_elf.h new file mode 100644 index 0000000000..7202cd8334 --- /dev/null +++ b/bsd-user/aarch64/target_arch_elf.h @@ -0,0 +1,165 @@ +/* + * ARM AArch64 ELF definitions for bsd-user + * + * Copyright (c) 2015 Stacey D. Son + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#ifndef TARGET_ARCH_ELF_H +#define TARGET_ARCH_ELF_H + +#include "target/arm/cpu-features.h" + +#define ELF_START_MMAP 0x80000000 +#define ELF_ET_DYN_LOAD_ADDR 0x100000 + +#define elf_check_arch(x) ((x) =3D=3D EM_AARCH64) + +#define ELF_CLASS ELFCLASS64 +#define ELF_DATA ELFDATA2LSB +#define ELF_ARCH EM_AARCH64 + +#define USE_ELF_CORE_DUMP +#define ELF_EXEC_PAGESIZE 4096 + +enum { + ARM_HWCAP_A64_FP =3D 1 << 0, + ARM_HWCAP_A64_ASIMD =3D 1 << 1, + ARM_HWCAP_A64_EVTSTRM =3D 1 << 2, + ARM_HWCAP_A64_AES =3D 1 << 3, + ARM_HWCAP_A64_PMULL =3D 1 << 4, + ARM_HWCAP_A64_SHA1 =3D 1 << 5, + ARM_HWCAP_A64_SHA2 =3D 1 << 6, + ARM_HWCAP_A64_CRC32 =3D 1 << 7, + ARM_HWCAP_A64_ATOMICS =3D 1 << 8, + ARM_HWCAP_A64_FPHP =3D 1 << 9, + ARM_HWCAP_A64_ASIMDHP =3D 1 << 10, + ARM_HWCAP_A64_CPUID =3D 1 << 11, + ARM_HWCAP_A64_ASIMDRDM =3D 1 << 12, + ARM_HWCAP_A64_JSCVT =3D 1 << 13, + ARM_HWCAP_A64_FCMA =3D 1 << 14, + ARM_HWCAP_A64_LRCPC =3D 1 << 15, + ARM_HWCAP_A64_DCPOP =3D 1 << 16, + ARM_HWCAP_A64_SHA3 =3D 1 << 17, + ARM_HWCAP_A64_SM3 =3D 1 << 18, + ARM_HWCAP_A64_SM4 =3D 1 << 19, + ARM_HWCAP_A64_ASIMDDP =3D 1 << 20, + ARM_HWCAP_A64_SHA512 =3D 1 << 21, + ARM_HWCAP_A64_SVE =3D 1 << 22, + ARM_HWCAP_A64_ASIMDFHM =3D 1 << 23, + ARM_HWCAP_A64_DIT =3D 1 << 24, + ARM_HWCAP_A64_USCAT =3D 1 << 25, + ARM_HWCAP_A64_ILRCPC =3D 1 << 26, + ARM_HWCAP_A64_FLAGM =3D 1 << 27, + ARM_HWCAP_A64_SSBS =3D 1 << 28, + ARM_HWCAP_A64_SB =3D 1 << 29, + ARM_HWCAP_A64_PACA =3D 1 << 30, + ARM_HWCAP_A64_PACG =3D 1UL << 31, + + ARM_HWCAP2_A64_DCPODP =3D 1 << 0, + ARM_HWCAP2_A64_SVE2 =3D 1 << 1, + ARM_HWCAP2_A64_SVEAES =3D 1 << 2, + ARM_HWCAP2_A64_SVEPMULL =3D 1 << 3, + ARM_HWCAP2_A64_SVEBITPERM =3D 1 << 4, + ARM_HWCAP2_A64_SVESHA3 =3D 1 << 5, + ARM_HWCAP2_A64_SVESM4 =3D 1 << 6, + ARM_HWCAP2_A64_FLAGM2 =3D 1 << 7, + ARM_HWCAP2_A64_FRINT =3D 1 << 8, + ARM_HWCAP2_A64_SVEI8MM =3D 1 << 9, + ARM_HWCAP2_A64_SVEF32MM =3D 1 << 10, + ARM_HWCAP2_A64_SVEF64MM =3D 1 << 11, + ARM_HWCAP2_A64_SVEBF16 =3D 1 << 12, + ARM_HWCAP2_A64_I8MM =3D 1 << 13, + ARM_HWCAP2_A64_BF16 =3D 1 << 14, + ARM_HWCAP2_A64_DGH =3D 1 << 15, + ARM_HWCAP2_A64_RNG =3D 1 << 16, + ARM_HWCAP2_A64_BTI =3D 1 << 17, + ARM_HWCAP2_A64_MTE =3D 1 << 18, +}; + +#define ELF_HWCAP get_elf_hwcap() +#define ELF_HWCAP2 get_elf_hwcap2() + +#define GET_FEATURE_ID(feat, hwcap) \ + do { if (cpu_isar_feature(feat, cpu)) { hwcaps |=3D hwcap; } } while (= 0) + +static uint32_t get_elf_hwcap(void) +{ + ARMCPU *cpu =3D ARM_CPU(thread_cpu); + uint32_t hwcaps =3D 0; + + hwcaps |=3D ARM_HWCAP_A64_FP; + hwcaps |=3D ARM_HWCAP_A64_ASIMD; + hwcaps |=3D ARM_HWCAP_A64_CPUID; + + /* probe for the extra features */ + + GET_FEATURE_ID(aa64_aes, ARM_HWCAP_A64_AES); + GET_FEATURE_ID(aa64_pmull, ARM_HWCAP_A64_PMULL); + GET_FEATURE_ID(aa64_sha1, ARM_HWCAP_A64_SHA1); + GET_FEATURE_ID(aa64_sha256, ARM_HWCAP_A64_SHA2); + GET_FEATURE_ID(aa64_sha512, ARM_HWCAP_A64_SHA512); + GET_FEATURE_ID(aa64_crc32, ARM_HWCAP_A64_CRC32); + GET_FEATURE_ID(aa64_sha3, ARM_HWCAP_A64_SHA3); + GET_FEATURE_ID(aa64_sm3, ARM_HWCAP_A64_SM3); + GET_FEATURE_ID(aa64_sm4, ARM_HWCAP_A64_SM4); + GET_FEATURE_ID(aa64_fp16, ARM_HWCAP_A64_FPHP | ARM_HWCAP_A64_ASIMDHP); + GET_FEATURE_ID(aa64_atomics, ARM_HWCAP_A64_ATOMICS); + GET_FEATURE_ID(aa64_rdm, ARM_HWCAP_A64_ASIMDRDM); + GET_FEATURE_ID(aa64_dp, ARM_HWCAP_A64_ASIMDDP); + GET_FEATURE_ID(aa64_fcma, ARM_HWCAP_A64_FCMA); + GET_FEATURE_ID(aa64_sve, ARM_HWCAP_A64_SVE); + GET_FEATURE_ID(aa64_pauth, ARM_HWCAP_A64_PACA | ARM_HWCAP_A64_PACG); + GET_FEATURE_ID(aa64_fhm, ARM_HWCAP_A64_ASIMDFHM); + GET_FEATURE_ID(aa64_jscvt, ARM_HWCAP_A64_JSCVT); + GET_FEATURE_ID(aa64_sb, ARM_HWCAP_A64_SB); + GET_FEATURE_ID(aa64_condm_4, ARM_HWCAP_A64_FLAGM); + GET_FEATURE_ID(aa64_dcpop, ARM_HWCAP_A64_DCPOP); + GET_FEATURE_ID(aa64_rcpc_8_3, ARM_HWCAP_A64_LRCPC); + GET_FEATURE_ID(aa64_rcpc_8_4, ARM_HWCAP_A64_ILRCPC); + + return hwcaps; +} + +static uint32_t get_elf_hwcap2(void) +{ + ARMCPU *cpu =3D ARM_CPU(thread_cpu); + uint32_t hwcaps =3D 0; + + GET_FEATURE_ID(aa64_dcpodp, ARM_HWCAP2_A64_DCPODP); + GET_FEATURE_ID(aa64_sve2, ARM_HWCAP2_A64_SVE2); + GET_FEATURE_ID(aa64_sve2_aes, ARM_HWCAP2_A64_SVEAES); + GET_FEATURE_ID(aa64_sve2_pmull128, ARM_HWCAP2_A64_SVEPMULL); + GET_FEATURE_ID(aa64_sve2_bitperm, ARM_HWCAP2_A64_SVEBITPERM); + GET_FEATURE_ID(aa64_sve2_sha3, ARM_HWCAP2_A64_SVESHA3); + GET_FEATURE_ID(aa64_sve2_sm4, ARM_HWCAP2_A64_SVESM4); + GET_FEATURE_ID(aa64_condm_5, ARM_HWCAP2_A64_FLAGM2); + GET_FEATURE_ID(aa64_frint, ARM_HWCAP2_A64_FRINT); + GET_FEATURE_ID(aa64_sve_i8mm, ARM_HWCAP2_A64_SVEI8MM); + GET_FEATURE_ID(aa64_sve_f32mm, ARM_HWCAP2_A64_SVEF32MM); + GET_FEATURE_ID(aa64_sve_f64mm, ARM_HWCAP2_A64_SVEF64MM); + GET_FEATURE_ID(aa64_sve_bf16, ARM_HWCAP2_A64_SVEBF16); + GET_FEATURE_ID(aa64_i8mm, ARM_HWCAP2_A64_I8MM); + GET_FEATURE_ID(aa64_bf16, ARM_HWCAP2_A64_BF16); + GET_FEATURE_ID(aa64_rndr, ARM_HWCAP2_A64_RNG); + GET_FEATURE_ID(aa64_bti, ARM_HWCAP2_A64_BTI); + GET_FEATURE_ID(aa64_mte, ARM_HWCAP2_A64_MTE); + + return hwcaps; +} + +#undef GET_FEATURE_ID + +#endif /* TARGET_ARCH_ELF_H */ diff --git a/bsd-user/aarch64/target_arch_vmparam.h b/bsd-user/aarch64/targ= et_arch_vmparam.h index dc66e1289b..0c35491970 100644 --- a/bsd-user/aarch64/target_arch_vmparam.h +++ b/bsd-user/aarch64/target_arch_vmparam.h @@ -65,4 +65,10 @@ static inline void set_second_rval(CPUARMState *state, a= bi_ulong retval2) { state->xregs[1] =3D retval2; /* XXX not really used on 64-bit arch */ } + +static inline abi_ulong get_second_rval(CPUARMState *state) +{ + return state->xregs[1]; +} + #endif /* TARGET_ARCH_VMPARAM_H */ --=20 2.34.1 From nobody Sun Nov 24 19:46:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1720379620; cv=none; d=zohomail.com; s=zohoarc; b=Zi0xqptYlgxr89VownyzZCLkdqR+K2lgqLNYcJ+YiCaV513OyYUNgati+CILSpSNBK6ErYEsW90S/7ITmXw8DGUcKVJIOuKrcY+q2JGl+hM9z9kiunVptkAa+jHwqk4l2Ry6BojF+sQE/g11tsU7pMgsVDWYLvWs0FAWSfk3vJY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1720379620; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=3mX/DMb2L404NJ60ga/gcKUOJORln93CqNAY7J2/D+Y=; b=M/fGHbuyEx597Dyvo1aq6vRGP0k+ijKJznOi5KwCDl6MS8emVdYgDPSzUiGZOi64AMB58WKi1p/T58LwD/yKRt0wTJ3HTCis4RmejWOnuykCZCxcvCRhNBLA3A888sY3QtH6TPMLxNZ/FxVVfUs7VfJGq0SmjwD5Ejgel9SBq0Y= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1720379620927575.4652605569916; Sun, 7 Jul 2024 12:13:40 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sQXId-0000mx-Rh; Sun, 07 Jul 2024 15:11:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sQXIb-0000mJ-Nc for qemu-devel@nongnu.org; Sun, 07 Jul 2024 15:11:49 -0400 Received: from mail-pl1-x636.google.com ([2607:f8b0:4864:20::636]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sQXIZ-00059E-Pr for qemu-devel@nongnu.org; Sun, 07 Jul 2024 15:11:49 -0400 Received: by mail-pl1-x636.google.com with SMTP id d9443c01a7336-1fb72eb3143so5584915ad.1 for ; Sun, 07 Jul 2024 12:11:47 -0700 (PDT) Received: from localhost.localdomain ([106.222.220.84]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1fac11d8a70sm172156725ad.118.2024.07.07.12.11.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Jul 2024 12:11:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1720379506; x=1720984306; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3mX/DMb2L404NJ60ga/gcKUOJORln93CqNAY7J2/D+Y=; b=mgkmeoCKLfBabgoxwJym3cP6yUwrYxJhQCerlDH2aKCbtUwej7F3V8CvjGqXUatE+K upGaxLb5p9cfJ29mMpnXh1sWTdzA2DPrwUHTUk6441Y1I0E4P+6hZ7pz9Qc2CIslmOvg OZ/ohCt7aS4mqvRXMAxUya5bEjq6GSOxc0dQvo97nBuF047KcpqbHHk3dZzC1dHqPudt qqwhUJgvLHRikJyMEv3SsW5tTZ8q2UfbbrFp2ySu0NxQSSyEZDrlu6v5+4wblS/9K1TQ a8ciSdLozji+yfPUqpXoxoRdezVaADKa55D6DDOPZznYhi5vRE8DLySeU+6qwg1a0U78 Kw/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1720379506; x=1720984306; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3mX/DMb2L404NJ60ga/gcKUOJORln93CqNAY7J2/D+Y=; b=g2xOLr2R+dhWHouEu7q38hwI1mSBmCcKJpRg4TrK1EDGBPHlyycwYQK0lMy+cB65NP POWO3jv9rs7ksrkpWP/RTn8yCmArCt6xbEBFXnAOqVbVo8NiG+KG3ctkH4rMM2/9UUwF Co/Wt47GYWNNGPRP3gku4yhxTty/hKixewDgWsVnZsm34wYTRSgJU2fmN8GJ6v+z2Ml0 QpZJCBCe+ECnVMIurtq524miZmgQ1TMnpsaDPwOpOx6BJEkG78PV9iZj+jwpmo2Ipoep pUoEgWpR0pRhl7eqkC45OtKvwi1XgvLd5XtFzMyDfzkXVu0uZfmQvGOyDnJVz8gLenvx NloA== X-Gm-Message-State: AOJu0YyYa0GGbwkALgqc+QMg1naCjnUu7/Qus/mVlcIidPIbwZ1wAHz8 Kf+l0euFdAuXWt8wG4YkK3BlNVaDhed8yeSXotFqGKzOJHXjrVQ8vjv6G6pY X-Google-Smtp-Source: AGHT+IFlQgkCtDIev81L4eKw6iKpyK3V3Spo9hDsTa3/fE6xjXeQXd5hWDNbHVvKElvEFlvj75oBtQ== X-Received: by 2002:a17:902:d2c1:b0:1fb:6121:dfc0 with SMTP id d9443c01a7336-1fb6121e339mr73778855ad.19.1720379505974; Sun, 07 Jul 2024 12:11:45 -0700 (PDT) From: Ajeet Singh X-Google-Original-From: Ajeet Singh To: qemu-devel@nongnu.org Cc: Warner Losh , Stacey Son , Ajeet Singh , Richard Henderson Subject: [PATCH v2 4/8] bsd-user:Add ARM AArch64 signal handling support Date: Mon, 8 Jul 2024 00:41:24 +0530 Message-Id: <20240707191128.10509-5-itachis@FreeBSD.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240707191128.10509-1-itachis@FreeBSD.org> References: <20240707191128.10509-1-itachis@FreeBSD.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=itachis6234@gmail.com; helo=mail-pl1-x636.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1720379622168100003 Content-Type: text/plain; charset="utf-8" From: Stacey Son Added sigcode setup function for signal trampoline which initializes a sequ= ence of instructions to handle signal returns and exits, copying this code to the target offset. Defined ARM AArch64 specific signal definitions including register indices = and sizes, and introduced structures to represent general purpose registers, floating = point registers, and machine context. Added function to set up signal handler arguments, populating register valu= es in `CPUARMState` based on the provided signal, signal frame, signal action, and frame addres= s. Signed-off-by: Stacey Son Signed-off-by: Ajeet Singh Signed-off-by: Warner Losh Co-authored-by: Warner Losh Reviewed-by: Richard Henderson --- bsd-user/aarch64/signal.c | 53 ++++++++++++++++ bsd-user/aarch64/target_arch_signal.h | 80 +++++++++++++++++++++++++ bsd-user/aarch64/target_arch_sigtramp.h | 48 +++++++++++++++ 3 files changed, 181 insertions(+) create mode 100644 bsd-user/aarch64/signal.c create mode 100644 bsd-user/aarch64/target_arch_signal.h create mode 100644 bsd-user/aarch64/target_arch_sigtramp.h diff --git a/bsd-user/aarch64/signal.c b/bsd-user/aarch64/signal.c new file mode 100644 index 0000000000..98861f9ab3 --- /dev/null +++ b/bsd-user/aarch64/signal.c @@ -0,0 +1,53 @@ +/* + * ARM AArch64 specific signal definitions for bsd-user + * + * Copyright (c) 2015 Stacey D. Son + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ +#include "qemu/osdep.h" + +#include "qemu.h" + +/* + * Compare to sendsig() in sys/arm64/arm64/machdep.c + * Assumes that target stack frame memory is locked. + */ +abi_long set_sigtramp_args(CPUARMState *regs, int sig, + struct target_sigframe *frame, + abi_ulong frame_addr, + struct target_sigaction *ka) +{ + /* + * Arguments to signal handler: + * x0 =3D signal number + * x1 =3D siginfo pointer + * x2 =3D ucontext pointer + * pc/elr =3D signal handler pointer + * sp =3D sigframe struct pointer + * lr =3D sigtramp at base of user stack + */ + + regs->xregs[0] =3D sig; + regs->xregs[1] =3D frame_addr + + offsetof(struct target_sigframe, sf_si); + regs->xregs[2] =3D frame_addr + + offsetof(struct target_sigframe, sf_uc); + + regs->pc =3D ka->_sa_handler; + regs->xregs[TARGET_REG_SP] =3D frame_addr; + regs->xregs[TARGET_REG_LR] =3D TARGET_PS_STRINGS - TARGET_SZSIGCODE; + + return 0; +} diff --git a/bsd-user/aarch64/target_arch_signal.h b/bsd-user/aarch64/targe= t_arch_signal.h new file mode 100644 index 0000000000..df17173316 --- /dev/null +++ b/bsd-user/aarch64/target_arch_signal.h @@ -0,0 +1,80 @@ +/* + * ARM AArch64 specific signal definitions for bsd-user + * + * Copyright (c) 2015 Stacey D. Son + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#ifndef TARGET_ARCH_SIGNAL_H +#define TARGET_ARCH_SIGNAL_H + +#include "cpu.h" + +#define TARGET_REG_X0 0 +#define TARGET_REG_X30 30 +#define TARGET_REG_X31 31 +#define TARGET_REG_LR TARGET_REG_X30 +#define TARGET_REG_SP TARGET_REG_X31 + +#define TARGET_INSN_SIZE 4 /* arm64 instruction size */ + +/* Size of the signal trampolin code. See _sigtramp(). */ +#define TARGET_SZSIGCODE ((abi_ulong)(9 * TARGET_INSN_SIZE)) + +/* compare to sys/arm64/include/_limits.h */ +#define TARGET_MINSIGSTKSZ (1024 * 4) /* min sig stack s= ize */ +#define TARGET_SIGSTKSZ (TARGET_MINSIGSTKSZ + 32768) /* recommended s= ize */ + +/* struct __mcontext in sys/arm64/include/ucontext.h */ + +struct target_gpregs { + uint64_t gp_x[30]; + uint64_t gp_lr; + uint64_t gp_sp; + uint64_t gp_elr; + uint32_t gp_spsr; + uint32_t gp_pad; +}; + +struct target_fpregs { + __uint128_t fp_q[32]; + uint32_t fp_sr; + uint32_t fp_cr; + uint32_t fp_flags; + uint32_t fp_pad; +}; + +struct target__mcontext { + struct target_gpregs mc_gpregs; + struct target_fpregs mc_fpregs; + uint32_t mc_flags; +#define TARGET_MC_FP_VALID 0x1 + uint32_t mc_pad; + uint64_t mc_spare[8]; +}; + +typedef struct target__mcontext target_mcontext_t; + +#define TARGET_MCONTEXT_SIZE 880 +#define TARGET_UCONTEXT_SIZE 960 + +#include "target_os_ucontext.h" + +struct target_sigframe { + target_siginfo_t sf_si; /* saved siginfo */ + target_ucontext_t sf_uc; /* saved ucontext */ +}; + +#endif /* TARGET_ARCH_SIGNAL_H */ diff --git a/bsd-user/aarch64/target_arch_sigtramp.h b/bsd-user/aarch64/tar= get_arch_sigtramp.h new file mode 100644 index 0000000000..8cdd33b621 --- /dev/null +++ b/bsd-user/aarch64/target_arch_sigtramp.h @@ -0,0 +1,48 @@ +/* + * ARM AArch64 sigcode for bsd-user + * + * Copyright (c) 2015 Stacey D. Son + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#ifndef TARGET_ARCH_SIGTRAMP_H +#define TARGET_ARCH_SIGTRAMP_H + +/* Compare to ENTRY(sigcode) in arm64/arm64/locore.S */ +static inline abi_long setup_sigtramp(abi_ulong offset, unsigned sigf_uc, + unsigned sys_sigreturn) +{ + int i; + uint32_t sys_exit =3D TARGET_FREEBSD_NR_exit; + + uint32_t sigtramp_code[] =3D { + /* 1 */ 0x910003e0, /* mov x0, sp */ + /* 2 */ 0x91000000 + (sigf_uc << 10), /* add x0, x0, #SIGF_UC */ + /* 3 */ 0xd2800000 + (sys_sigreturn << 5) + 0x8, /* mov x8, #SYS_sigre= turn */ + /* 4 */ 0xd4000001, /* svc #0 */ + /* 5 */ 0xd2800028 + (sys_exit << 5) + 0x8, /* mov x8, #SYS_exit */ + /* 6 */ 0xd4000001, /* svc #0 */ + /* 7 */ 0x17fffffc, /* b -4 */ + /* 8 */ sys_sigreturn, + /* 9 */ sys_exit + }; + + for (i =3D 0; i < 9; i++) { + tswap32s(&sigtramp_code[i]); + } + + return memcpy_to_target(offset, sigtramp_code, TARGET_SZSIGCODE); +} +#endif /* TARGET_ARCH_SIGTRAMP_H */ --=20 2.34.1 From nobody Sun Nov 24 19:46:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1720379549; cv=none; d=zohomail.com; s=zohoarc; b=FdbF+xoZObav33gcJNA89frakTP8GBo7n0CsIAI0PJHdFGDygfCFg93mQHToWI3g11bO+/0ixkPdasGjKZDeHwS4ez8loG6R9HIsPhj5hTKJgGrf2bMsnc7bdmtkefx9o5b9tYEmtS5TYr50/Fbk8UDmzEmvTz9BmaToaTxm+Sc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1720379549; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=7QeYYhSPAIOJyKkxryN3Nk246i89++ucyqIxnORISd4=; b=noP3YvvAEX9J7RhhKBA1VNdriGNIv9XSJ7qqjqZkn4uD+LvpCF/qc7IMhX4CLv6pzehHP4nr9lx2BB/LDcDcIWNX7nZrbiT5wrxVZTHVtmcg4JRo7Q+erfK1tK+SzKGotMAGIFXAsHWEnDhg96MrEPvrBDunJVeCQBzOq+k1tQc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1720379549980372.6415752855462; Sun, 7 Jul 2024 12:12:29 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sQXIe-0000my-0y; Sun, 07 Jul 2024 15:11:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sQXId-0000mm-8b for qemu-devel@nongnu.org; Sun, 07 Jul 2024 15:11:51 -0400 Received: from mail-pl1-x632.google.com ([2607:f8b0:4864:20::632]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sQXIb-00059a-Pg for qemu-devel@nongnu.org; Sun, 07 Jul 2024 15:11:51 -0400 Received: by mail-pl1-x632.google.com with SMTP id d9443c01a7336-1f65a3abd01so22586825ad.3 for ; Sun, 07 Jul 2024 12:11:49 -0700 (PDT) Received: from localhost.localdomain ([106.222.220.84]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1fac11d8a70sm172156725ad.118.2024.07.07.12.11.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Jul 2024 12:11:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1720379508; x=1720984308; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7QeYYhSPAIOJyKkxryN3Nk246i89++ucyqIxnORISd4=; b=OdjFWn5wM4rSaCxbrSNGokrwhJ0IX5Bz2jwNH4VRMb7LDxHeLPMFiIsaAUstQyxHex EELjCMdgREHiJghrs1qrY5SVxNQ+aOLrX8j6YTj7ZT1cRz3/2W+hNhkR7RzAtzMPav4b dsMvrjmUZpsQ6fZpvU+wY7lfW4gcK4Wt1zmXx8YqcCLqF7OEvpfu1RwbUtQoCvQ5c1HG klcMeDttzXHwDWL1f+b5Xey8hZxckhyCgYketYr608Rbi2C+uYYIN0M+0QOZyI6crfdl 3SSSzgnmG1xptrkuu6Dqa1mJb9wceyBPQjnvuMxhdNqwyPmG7aVpP4aU/eKGDUz8cYyH /9aQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1720379508; x=1720984308; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7QeYYhSPAIOJyKkxryN3Nk246i89++ucyqIxnORISd4=; b=sOAAL3tF/JoPDYXfUthRX3fi9G7jRCvbQiPW0nCE1VzPGXFQGr1m0bNXGcdstaW6JD DP0ry+W4g6ngGft1NNMc9PFvwV4FhmZr19qvINkV3LQf61mYADH+7rGYJcp3wG9RynMD Q5nGCHj8IcE7/DJdnO5heH+GSsy9A95RuM9/8hpU4aHouLECANggfH3AZxG4nYupm54T S5KFuHRYvrOc3jVps2o5Ssju2KOcO6koXQWunIs8f8mUAZIjHeAk72jh5Y/jUmu2XjEE HX9WLG//X+V5aahdt15aN6KIZMYoFVMPvM2ViWeQMKOY84caYogoOdEV05Jnmz8SUMG5 52Sw== X-Gm-Message-State: AOJu0Yx9RbuZYjMNXYfwMy6+ki/zlLW2uLazzxlGyVBzgjzS6P0IVNKm sPsQ4Wk+2u/AiIf4uAECF74Aa+0mRYOR3Gtz2rTAuiEpgAnqob5jVFNv0Pt9 X-Google-Smtp-Source: AGHT+IEOpgOprySwIe49Tz7iuItn+AUFtDpWnuVdEhm6ZbquG9KwJuDeIej/9Edzbwcron4XC3eGCw== X-Received: by 2002:a17:903:120b:b0:1f6:ed74:b4e3 with SMTP id d9443c01a7336-1fb33e0511amr115189115ad.3.1720379508057; Sun, 07 Jul 2024 12:11:48 -0700 (PDT) From: Ajeet Singh X-Google-Original-From: Ajeet Singh To: qemu-devel@nongnu.org Cc: Warner Losh , Stacey Son , Ajeet Singh , Kyle Evans Subject: [PATCH v2 5/8] bsd-user:Add get_mcontext function for ARM AArch64 Date: Mon, 8 Jul 2024 00:41:25 +0530 Message-Id: <20240707191128.10509-6-itachis@FreeBSD.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240707191128.10509-1-itachis@FreeBSD.org> References: <20240707191128.10509-1-itachis@FreeBSD.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=itachis6234@gmail.com; helo=mail-pl1-x632.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1720379552034100007 Content-Type: text/plain; charset="utf-8" From: Stacey Son function to retrieve machine context,it populates the provided target_mcontext_t structure with information from the CPUARMState registers. Signed-off-by: Stacey Son Signed-off-by: Ajeet Singh Co-authored-by: Kyle Evans Reviewed-by: Richard Henderson --- bsd-user/aarch64/signal.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/bsd-user/aarch64/signal.c b/bsd-user/aarch64/signal.c index 98861f9ab3..ab3bf8558a 100644 --- a/bsd-user/aarch64/signal.c +++ b/bsd-user/aarch64/signal.c @@ -51,3 +51,33 @@ abi_long set_sigtramp_args(CPUARMState *regs, int sig, =20 return 0; } + +/* + * Compare to get_mcontext() in arm64/arm64/machdep.c + * Assumes that the memory is locked if mcp points to user memory. + */ +abi_long get_mcontext(CPUARMState *regs, target_mcontext_t *mcp, int flags) +{ + int err =3D 0, i; + uint64_t *gr =3D mcp->mc_gpregs.gp_x; + + mcp->mc_gpregs.gp_spsr =3D pstate_read(regs); + if (flags & TARGET_MC_GET_CLEAR_RET) { + gr[0] =3D 0UL; + mcp->mc_gpregs.gp_spsr &=3D ~CPSR_C; + } else { + gr[0] =3D tswap64(regs->xregs[0]); + } + + for (i =3D 1; i < 30; i++) { + gr[i] =3D tswap64(regs->xregs[i]); + } + + mcp->mc_gpregs.gp_sp =3D tswap64(regs->xregs[TARGET_REG_SP]); + mcp->mc_gpregs.gp_lr =3D tswap64(regs->xregs[TARGET_REG_LR]); + mcp->mc_gpregs.gp_elr =3D tswap64(regs->pc); + + /* XXX FP? */ + + return err; +} --=20 2.34.1 From nobody Sun Nov 24 19:46:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1720379567; cv=none; d=zohomail.com; s=zohoarc; b=cls66t0XYViA6y1UluaD8ySHkZ7rSycrHZy5PrmPbm7SovP/5XYXDgRf9+Vv6b7DA2UDDf2lW5eH6FXbMDJFBkrHyf9+JTR5aTUxeb90I8YIyVrMJ8BdQ3AkAIOGEMlhX7iAdycTeUfvenK3VudXEIQpK7CLp/kegD3XEzK1iwU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1720379567; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=tzZW7S7trkqr70JQTEMEt+xFl2Pbm9pRqeFrftAZXeU=; b=kko1Q4mCwdtNs74mIiRGWvD9PqSFXZ2zdoV4vrwssNVOZHEIV/5g62PhTN8TcetXXVbV/jGhAKwBDBNDDtDMsT93JQUNTcCRRdh7Y9tKTXC7E6fL97ocCfrM0RAvyd7i0dkyhNR/9ePhKeFR8amxogAFO3B29xcMpBDviWF615g= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1720379567230447.5085203719218; Sun, 7 Jul 2024 12:12:47 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sQXIf-0000nk-Om; Sun, 07 Jul 2024 15:11:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sQXIe-0000n2-LE for qemu-devel@nongnu.org; Sun, 07 Jul 2024 15:11:52 -0400 Received: from mail-oi1-x22c.google.com ([2607:f8b0:4864:20::22c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sQXId-00059m-6Y for qemu-devel@nongnu.org; Sun, 07 Jul 2024 15:11:52 -0400 Received: by mail-oi1-x22c.google.com with SMTP id 5614622812f47-3d932f991f6so44207b6e.1 for ; Sun, 07 Jul 2024 12:11:50 -0700 (PDT) Received: from localhost.localdomain ([106.222.220.84]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1fac11d8a70sm172156725ad.118.2024.07.07.12.11.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Jul 2024 12:11:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1720379510; x=1720984310; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=tzZW7S7trkqr70JQTEMEt+xFl2Pbm9pRqeFrftAZXeU=; b=LMCjp1HnhgWul6k32vvD0eC6njqViOJK8A6opiyq+SuzoBaZbVeLmNPAUjxcER3vIV LMnGhUA7fxl3YJNRutewf9PUPTFq4jG/lCODGbJnVl/QzkqEKuS0J1J1rfl7Bxdd1TEr QS+8UVHxS8eqqaWivLB8QN/a7U66GLnCDmT5YcrA65E0KTJaHFwpMICjs3JBU/MrZFLb jfMf3LSpwcT0BYcIZWhxSgc5Hp3gg2sWy3G9/9yWcVZkBrYIz0nhP29J/6FSncVE9diZ QhK2j2NfbdxMf1Eqv9kxmu6rD0o1xj5koF64rqzBEQWE+zvH+ySNG/nLYDfATz0Fwssx TjZw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1720379510; x=1720984310; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=tzZW7S7trkqr70JQTEMEt+xFl2Pbm9pRqeFrftAZXeU=; b=U3JONzRTaUVhfNuJz76jdjAK6/un/WnBQZMPh6GO9S/ijH8glglz9/0PN4APulNNyT lfPPFq5sRAXkp/leNf5nqaBqq44xDwBt6Xszygh148eYgsGWvDDTBAT3Grvw9vaLlBWd loQbndQH6qbP2B9KElbTymdLRoXWJHaaozGeZ+jr6ZoQWl/6xjba7Kq0MvexNCc/KIbe pdHBf4dT1TSOFwcaw1fCqJrTX5xPCI3BJycgXkhMCwOgo/lSymIHvs/lLP0PLn3vK2Gx 6RNc/DN5f79udrTRDv5UsE1MrWo9JugSviBcZyzATOhP8yFVrIp2PLSSCgqgqXTKphEY Z5SQ== X-Gm-Message-State: AOJu0YzDRoXiQcVWqcv+zpvN5IXP+rRcfO2gynWc4kX6qf86NBy23I3r GysnPcICnAJORZyszIgpg+RtLvMQt8AOOowr7Oj+CVRjuKTky9LK97VG8LOx X-Google-Smtp-Source: AGHT+IGIM+wISClL3BYSAWW5tNb+206wRD4X5lJpkhYL7VdQzuueswRjaLFFiTHwc5lFCYj+nCC7Yw== X-Received: by 2002:a05:6808:210e:b0:3d5:6504:6713 with SMTP id 5614622812f47-3d914e9df47mr13520889b6e.43.1720379509847; Sun, 07 Jul 2024 12:11:49 -0700 (PDT) From: Ajeet Singh X-Google-Original-From: Ajeet Singh To: qemu-devel@nongnu.org Cc: Warner Losh , Ajeet Singh , Richard Henderson Subject: [PATCH v2 6/8] bsd-user:Add setup_sigframe_arch function for ARM AArch64 Date: Mon, 8 Jul 2024 00:41:26 +0530 Message-Id: <20240707191128.10509-7-itachis@FreeBSD.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240707191128.10509-1-itachis@FreeBSD.org> References: <20240707191128.10509-1-itachis@FreeBSD.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22c; envelope-from=itachis6234@gmail.com; helo=mail-oi1-x22c.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1720379568008100004 Content-Type: text/plain; charset="utf-8" From: Warner Losh The function utilizes the `get_mcontext` function to retrieve the machine context for the current CPUARMState Signed-off-by: Warner Losh Signed-off-by: Ajeet Singh Reviewed-by: Richard Henderson --- bsd-user/aarch64/signal.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/bsd-user/aarch64/signal.c b/bsd-user/aarch64/signal.c index ab3bf8558a..43c886e603 100644 --- a/bsd-user/aarch64/signal.c +++ b/bsd-user/aarch64/signal.c @@ -81,3 +81,17 @@ abi_long get_mcontext(CPUARMState *regs, target_mcontext= _t *mcp, int flags) =20 return err; } + +/* + * Compare to arm64/arm64/exec_machdep.c sendsig() + * Assumes that the memory is locked if frame points to user memory. + */ +abi_long setup_sigframe_arch(CPUARMState *env, abi_ulong frame_addr, + struct target_sigframe *frame, int flags) +{ + target_mcontext_t *mcp =3D &frame->sf_uc.uc_mcontext; + + get_mcontext(env, mcp, flags); + return 0; +} + --=20 2.34.1 From nobody Sun Nov 24 19:46:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1720379583; cv=none; d=zohomail.com; s=zohoarc; b=lK17JMsGTbivfDw6tFQ+HZ4rG8boy2apoRytfDfAsS2WG8spLZVHvpbtR1O9qQgkXTkO8ME11zArG75z3PsizZtOrXjXHYU03nlkCGjLdLu8TmJlioIS+qC2pKzIJ/5xyQBAzwmsqcx6gVSVWLHQZtncUnXiA9KkTX2V5N3/eiU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1720379583; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=v5fjvNTx+vSPFZHp2emZLnu0OQ08Pqx5zQgJemqgRQ0=; b=J8XX5Zk1b5C7aq2GLXDbecEHUFVKgmOr50G3TdMIc/LJ5MIVqCkfhAid08g4GCKV44iE+1sPePvyA3inxaYAPj++CojvFFvs2jJ2JH66ETtS/i7MDGDnXqQobKo+cjllJWQnMD0FM+jYq+XgeT8Uyb5yCBLnayx4b+KU0n8Bcuc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 172037958314873.27751408851645; Sun, 7 Jul 2024 12:13:03 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sQXIh-0000oB-Kz; Sun, 07 Jul 2024 15:11:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sQXIg-0000o2-LO for qemu-devel@nongnu.org; Sun, 07 Jul 2024 15:11:54 -0400 Received: from mail-oi1-x233.google.com ([2607:f8b0:4864:20::233]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sQXIf-00059z-73 for qemu-devel@nongnu.org; Sun, 07 Jul 2024 15:11:54 -0400 Received: by mail-oi1-x233.google.com with SMTP id 5614622812f47-3d92bbadfd6so461083b6e.3 for ; Sun, 07 Jul 2024 12:11:52 -0700 (PDT) Received: from localhost.localdomain ([106.222.220.84]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1fac11d8a70sm172156725ad.118.2024.07.07.12.11.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Jul 2024 12:11:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1720379512; x=1720984312; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=v5fjvNTx+vSPFZHp2emZLnu0OQ08Pqx5zQgJemqgRQ0=; b=F1uLfl/SSpcI8IonT5DHLDho7DF9AUzy9NPsDkbwYDEQZGpfC0V36N39cDbBs8+n5l SC08vSt1b/xKgvxuhcHWZi/vKwRkiqS166+Cgf3w6ySkB9sc3a4meTW/JdYLDN/LfJvm FbelrbwzuO9xs1XXnDKhDgCTnpmS9Y9BJ+2XXvAme2NL+L9V8u16lvh2pzpmuCRW5koB P3291G5bjGdFxa0oEM33/NUCpnxxuTk2Lw5kCkTrpLEjd9BL0+wLbZKyW4hxDIA5Qici Geh8Wh8TzRBynwKR8TFme/BDMFkco9hbMGIIo9o8EKt60CeU2IWxqJlmhwpFiZTM/kB8 kijg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1720379512; x=1720984312; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=v5fjvNTx+vSPFZHp2emZLnu0OQ08Pqx5zQgJemqgRQ0=; b=adSPosAld9S+trO6RCLimZ1jqI8svINnersGV0otz+q+tTO7GdwZn4IWGqkdyzU0fk 2cZtA7qt6czF9MH1cAuOArhgvnygrHwmEtQ+DdVgiacKujzq1J+ua02NJeBCykZYWmTx 9NRpzZYmbkC/MctXi/qCOhsVKQ/Dz/LzEXJnyltVh8c3/mW3uvu8ma87pBvkxUe9sPSt Q9a7PVzkPQ98WOGVY95YAgFaFUOjrMvFSlPLRbs/eShcFgZMLObOo/fE4SLujwfHPwO6 ZUAmvxU00wDWnn2uSw+vHpBBPjCWP565nnYucsFVAk6DsoXy6gGzYvk8Wk4DAgsLzng6 SbAA== X-Gm-Message-State: AOJu0Yyroa7UwBU+PtoZ3m1ShA+DeUZ1Ph1vhsrV0UvH84Su2OorLlMR 3AN3i+LuZEMOyhoTqukw39oa/ym4xWR6QjAHntJe6giNVLdmhLd/P5D41O36 X-Google-Smtp-Source: AGHT+IEXSu2N8jPpnw7zLKIx57cf0AKYgpXqa7y3MKyXHXh5o3Kh+W3KlgofBf/eahjKbvDm5mBGHg== X-Received: by 2002:a05:6808:1705:b0:3d6:2fc8:2553 with SMTP id 5614622812f47-3d914eabe84mr11526335b6e.52.1720379511656; Sun, 07 Jul 2024 12:11:51 -0700 (PDT) From: Ajeet Singh X-Google-Original-From: Ajeet Singh To: qemu-devel@nongnu.org Cc: Warner Losh , Stacey Son , Ajeet Singh Subject: [PATCH v2 7/8] bsd-user:Add set_mcontext function for ARM AArch64 Date: Mon, 8 Jul 2024 00:41:27 +0530 Message-Id: <20240707191128.10509-8-itachis@FreeBSD.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240707191128.10509-1-itachis@FreeBSD.org> References: <20240707191128.10509-1-itachis@FreeBSD.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::233; envelope-from=itachis6234@gmail.com; helo=mail-oi1-x233.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1720379584029100001 Content-Type: text/plain; charset="utf-8" From: Stacey Son The function copies register values from the provided target_mcontext_t structure to the CPUARMState registers. Note:FP is unfinished upstream but will be a separate commit coming soon. Signed-off-by: Stacey Son Signed-off-by: Ajeet Singh Reviewed-by: Richard Henderson --- bsd-user/aarch64/signal.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/bsd-user/aarch64/signal.c b/bsd-user/aarch64/signal.c index 43c886e603..13faac8ce6 100644 --- a/bsd-user/aarch64/signal.c +++ b/bsd-user/aarch64/signal.c @@ -95,3 +95,25 @@ abi_long setup_sigframe_arch(CPUARMState *env, abi_ulong= frame_addr, return 0; } =20 +/* + * Compare to set_mcontext() in arm64/arm64/machdep.c + * Assumes that the memory is locked if frame points to user memory. + */ +abi_long set_mcontext(CPUARMState *regs, target_mcontext_t *mcp, int srfla= g) +{ + int err =3D 0, i; + const uint64_t *gr =3D mcp->mc_gpregs.gp_x; + + for (i =3D 0; i < 30; i++) { + regs->xregs[i] =3D tswap64(gr[i]); + } + + regs->xregs[TARGET_REG_SP] =3D tswap64(mcp->mc_gpregs.gp_sp); + regs->xregs[TARGET_REG_LR] =3D tswap64(mcp->mc_gpregs.gp_lr); + regs->pc =3D mcp->mc_gpregs.gp_elr; + pstate_write(regs, mcp->mc_gpregs.gp_spsr); + + /* XXX FP? */ + + return err; +} --=20 2.34.1 From nobody Sun Nov 24 19:46:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1720379549; cv=none; d=zohomail.com; s=zohoarc; b=OMyTCKePob5KwJwigxP5NM2d3N6WN7VjRir6XmlVUNj7XiAGr8xu4R+Rtk8oOkRmwJJqhLI1zUbUA9RT2KZ0xLER0+wDK3GVdwSiTfrGI5qG4KG1FwfLiXDLp9WyNA3EH1mzmRpGePMUXVhDNx+KU26oDSLjAqeHbGdv9xSv2AU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1720379549; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=xg27xgnLi4xIfFOcGoXylyDerzXo9C4ECzAbWCiXwIs=; b=fWRHd4s2F4K7AAl8GLLttPsGklGCB6M0Klc28rG33jQZD3JOWALy3LTYSyfwosALdHlnfHIVMvIxsHHUhFPMQGyYJA6myfn8Eqsd11z72yjfirE1CSBYr0Md6dPwF3spxptKr+eN/wwUyAVZLZbLcCtaiyTmsSVMn2fQVG3TNsw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1720379549652789.5420303406994; Sun, 7 Jul 2024 12:12:29 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sQXIk-0000ou-Dt; Sun, 07 Jul 2024 15:11:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sQXIi-0000oT-NU for qemu-devel@nongnu.org; Sun, 07 Jul 2024 15:11:56 -0400 Received: from mail-pl1-x630.google.com ([2607:f8b0:4864:20::630]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sQXIg-0005AC-V4 for qemu-devel@nongnu.org; Sun, 07 Jul 2024 15:11:56 -0400 Received: by mail-pl1-x630.google.com with SMTP id d9443c01a7336-1fb05b0be01so18836575ad.2 for ; Sun, 07 Jul 2024 12:11:54 -0700 (PDT) Received: from localhost.localdomain ([106.222.220.84]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1fac11d8a70sm172156725ad.118.2024.07.07.12.11.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Jul 2024 12:11:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1720379513; x=1720984313; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xg27xgnLi4xIfFOcGoXylyDerzXo9C4ECzAbWCiXwIs=; b=NJYYOXUCC2zJ/5I8HntuqygmN5LY6JXGksE9PkGOtzHbquitntfBM2N5qpW0Xh0MIu onD5jHMiFIvpFp0itqH0ObQTO27wfuUwGA7FWE47kicJcUbcHfcvxZvVXLno7TOrqcnE Ku2SdFKxqZgJijCh/p7VAh8ZTiFH0R/hyFuxiPCCvNmMimM2nD1NsE60JjrDVdUZB23U P2AGPNdKz0pYMOcDV3NYjCm2NoC/NKhgPcxEGAn/ecRhOK+OfarbVkKwaB/0bbUywjVI yhRG5H4jDNNdIccwrQfJ8GdAUhSuUiCaJIhWL+m1VZwSXgwkDhfW3cseK8Zo3RX9xv/U /Uhw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1720379513; x=1720984313; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xg27xgnLi4xIfFOcGoXylyDerzXo9C4ECzAbWCiXwIs=; b=NoNiNsILprM5+yWrxM7c84lKCTCT0mhESZkJbp54XF4jeUJ1nw/HMy/IUvYt3TcnBv tALc6e8CFhjGl6jSgSZ/j+K01xtQsqkwRtzDwPHs9hcKAEy04NFVtC0pv7VMaofdnjwy +5fQCsESnrbN5O5lc8ZWWG3TE3kGyxSPGYlX6wPB+XnU3vjRvfwId01GBG8UAYj/r7eK L+lU/765GOGhEzY8qjBChCij98dXYn2PkSqILWHfjBidrWmQA3fglcWPUq6txF0Zb0uM a91LaKcKmtFvgR9EJbaLQACj7QphDTGEBv9YsQfyZTCVdjUURBvnIqR7798REsD0v/eJ 9WBA== X-Gm-Message-State: AOJu0YwYUzH13jAH7Cu4ycRl/gpdg9BEldOmXZs45YSOp7FkR7n4Ylic K0VJQVO5Y0W6SeJSSf0im8iu1Anr2TOTfLxjeUgcILnWllxVm/n5NzVYD26j X-Google-Smtp-Source: AGHT+IEEoH0C9spPE58kwVarAh8KAIyTPsXjq8q7V0TLneUbUXCeurdn5sx+Vddq+nituF8jAqLXRg== X-Received: by 2002:a17:902:da86:b0:1fb:80a3:5833 with SMTP id d9443c01a7336-1fb80a35b3emr29724305ad.47.1720379513456; Sun, 07 Jul 2024 12:11:53 -0700 (PDT) From: Ajeet Singh X-Google-Original-From: Ajeet Singh To: qemu-devel@nongnu.org Cc: Warner Losh , Stacey Son , Ajeet Singh Subject: [PATCH v2 8/8] bsd-user:Add AArch64 improvements and signal handling functions Date: Mon, 8 Jul 2024 00:41:28 +0530 Message-Id: <20240707191128.10509-9-itachis@FreeBSD.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240707191128.10509-1-itachis@FreeBSD.org> References: <20240707191128.10509-1-itachis@FreeBSD.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=itachis6234@gmail.com; helo=mail-pl1-x630.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1720379551230100001 Content-Type: text/plain; charset="utf-8" From: Stacey Son Added get_ucontext_sigreturn function to check processor state ensuring cur= rent execution mode is EL0 and no flags indicating interrupts or exceptions are set. Updated AArch64 code to use CF directly without reading/writing the entire = processor state, improving efficiency. Changed FP data structures to use Int128 instead of __uint128_t, leveraging= QEMU's generic mechanism for referencing this type. Signed-off-by: Stacey Son Signed-off-by: Ajeet Singh Signed-off-by: Warner Losh Reviewed-by: Richard Henderson --- bsd-user/aarch64/signal.c | 20 +++++++++++++++++++- bsd-user/aarch64/target_arch_cpu.h | 7 ++----- bsd-user/aarch64/target_arch_reg.h | 2 +- bsd-user/aarch64/target_arch_signal.h | 2 +- bsd-user/qemu.h | 3 +++ 5 files changed, 26 insertions(+), 8 deletions(-) diff --git a/bsd-user/aarch64/signal.c b/bsd-user/aarch64/signal.c index 13faac8ce6..6bc73a798f 100644 --- a/bsd-user/aarch64/signal.c +++ b/bsd-user/aarch64/signal.c @@ -21,7 +21,7 @@ #include "qemu.h" =20 /* - * Compare to sendsig() in sys/arm64/arm64/machdep.c + * Compare to sendsig() in sys/arm64/arm64/exec_machdep.c * Assumes that target stack frame memory is locked. */ abi_long set_sigtramp_args(CPUARMState *regs, int sig, @@ -117,3 +117,21 @@ abi_long set_mcontext(CPUARMState *regs, target_mconte= xt_t *mcp, int srflag) =20 return err; } + +/* Compare to sys_sigreturn() in arm64/arm64/machdep.c */ +abi_long get_ucontext_sigreturn(CPUARMState *regs, abi_ulong target_sf, + abi_ulong *target_uc) +{ + uint32_t pstate =3D pstate_read(regs); + + *target_uc =3D 0; + + if ((pstate & PSTATE_M) !=3D PSTATE_MODE_EL0t || + (pstate & (PSTATE_F | PSTATE_I | PSTATE_A | PSTATE_D)) !=3D 0) { + return -TARGET_EINVAL; + } + + *target_uc =3D target_sf; + + return 0; +} diff --git a/bsd-user/aarch64/target_arch_cpu.h b/bsd-user/aarch64/target_a= rch_cpu.h index 4e950305d3..408aef2bb5 100644 --- a/bsd-user/aarch64/target_arch_cpu.h +++ b/bsd-user/aarch64/target_arch_cpu.h @@ -47,7 +47,6 @@ static inline void target_cpu_loop(CPUARMState *env) CPUState *cs =3D env_cpu(env); int trapnr, ec, fsc, si_code, si_signo; uint64_t code, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8; - uint32_t pstate; abi_long ret; =20 for (;;) { @@ -87,18 +86,16 @@ static inline void target_cpu_loop(CPUARMState *env) * The carry bit is cleared for no error; set for error. * See arm64/arm64/vm_machdep.c cpu_set_syscall_retval() */ - pstate =3D pstate_read(env); if (ret >=3D 0) { - pstate &=3D ~PSTATE_C; + env->CF =3D 0; env->xregs[0] =3D ret; } else if (ret =3D=3D -TARGET_ERESTART) { env->pc -=3D 4; break; } else if (ret !=3D -TARGET_EJUSTRETURN) { - pstate |=3D PSTATE_C; + env->CF =3D 1; env->xregs[0] =3D -ret; } - pstate_write(env, pstate); break; =20 case EXCP_INTERRUPT: diff --git a/bsd-user/aarch64/target_arch_reg.h b/bsd-user/aarch64/target_a= rch_reg.h index 5c7154f0c1..b53302e7f7 100644 --- a/bsd-user/aarch64/target_arch_reg.h +++ b/bsd-user/aarch64/target_arch_reg.h @@ -31,7 +31,7 @@ typedef struct target_reg { } target_reg_t; =20 typedef struct target_fpreg { - __uint128_t fp_q[32]; + Int128 fp_q[32]; uint32_t fp_sr; uint32_t fp_cr; } target_fpreg_t; diff --git a/bsd-user/aarch64/target_arch_signal.h b/bsd-user/aarch64/targe= t_arch_signal.h index df17173316..bff752a67a 100644 --- a/bsd-user/aarch64/target_arch_signal.h +++ b/bsd-user/aarch64/target_arch_signal.h @@ -49,7 +49,7 @@ struct target_gpregs { }; =20 struct target_fpregs { - __uint128_t fp_q[32]; + Int128 fp_q[32]; uint32_t fp_sr; uint32_t fp_cr; uint32_t fp_flags; diff --git a/bsd-user/qemu.h b/bsd-user/qemu.h index 9d2fc7148e..3736c41786 100644 --- a/bsd-user/qemu.h +++ b/bsd-user/qemu.h @@ -17,6 +17,9 @@ #ifndef QEMU_H #define QEMU_H =20 +#include + +#include "qemu/int128.h" #include "cpu.h" #include "qemu/units.h" #include "exec/cpu_ldst.h" --=20 2.34.1