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Fri, 05 Jul 2024 08:31:08 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: Gustavo Romero , Manos Pitsidianakis , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Laurent Vivier Subject: [PULL 35/40] target/arm: Factor out code for setting MTE TCF0 field Date: Fri, 5 Jul 2024 16:30:47 +0100 Message-Id: <20240705153052.1219696-36-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240705153052.1219696-1-alex.bennee@linaro.org> References: <20240705153052.1219696-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::532; envelope-from=alex.bennee@linaro.org; helo=mail-ed1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1720193625838100003 From: Gustavo Romero Factor out the code used for setting the MTE TCF0 field from the prctl code into a convenient function. Other subsystems, like gdbstub, need to set this field as well, so keep it as a separate function to avoid duplication and ensure consistency in how this field is set across the board. Signed-off-by: Gustavo Romero Message-Id: <20240628050850.536447-7-gustavo.romero@linaro.org> [AJB: clean-up includes, move MTE defines] Reviewed-by: Manos Pitsidianakis Signed-off-by: Alex Benn=C3=A9e Message-Id: <20240705084047.857176-36-alex.bennee@linaro.org> diff --git a/linux-user/aarch64/mte_user_helper.h b/linux-user/aarch64/mte_= user_helper.h new file mode 100644 index 0000000000..8685e5175a --- /dev/null +++ b/linux-user/aarch64/mte_user_helper.h @@ -0,0 +1,32 @@ +/* + * ARM MemTag convenience functions. + * + * This code is licensed under the GNU GPL v2 or later. + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ + +#ifndef AARCH64_MTE_USER_HELPER_H +#define AARCH64_MTE USER_HELPER_H + +#ifndef PR_MTE_TCF_SHIFT +# define PR_MTE_TCF_SHIFT 1 +# define PR_MTE_TCF_NONE (0UL << PR_MTE_TCF_SHIFT) +# define PR_MTE_TCF_SYNC (1UL << PR_MTE_TCF_SHIFT) +# define PR_MTE_TCF_ASYNC (2UL << PR_MTE_TCF_SHIFT) +# define PR_MTE_TCF_MASK (3UL << PR_MTE_TCF_SHIFT) +# define PR_MTE_TAG_SHIFT 3 +# define PR_MTE_TAG_MASK (0xffffUL << PR_MTE_TAG_SHIFT) +#endif + +/** + * arm_set_mte_tcf0 - Set TCF0 field in SCTLR_EL1 register + * @env: The CPU environment + * @value: The value to be set for the Tag Check Fault in EL0 field. + * + * Only SYNC and ASYNC modes can be selected. If ASYMM mode is given, the = SYNC + * mode is selected instead. So, there is no way to set the ASYMM mode. + */ +void arm_set_mte_tcf0(CPUArchState *env, abi_long value); + +#endif /* AARCH64_MTE_USER_HELPER_H */ diff --git a/linux-user/aarch64/target_prctl.h b/linux-user/aarch64/target_= prctl.h index aa8e203c15..ed75b9e4b5 100644 --- a/linux-user/aarch64/target_prctl.h +++ b/linux-user/aarch64/target_prctl.h @@ -7,6 +7,7 @@ #define AARCH64_TARGET_PRCTL_H =20 #include "target/arm/cpu-features.h" +#include "mte_user_helper.h" =20 static abi_long do_prctl_sve_get_vl(CPUArchState *env) { @@ -173,26 +174,7 @@ static abi_long do_prctl_set_tagged_addr_ctrl(CPUArchS= tate *env, abi_long arg2) env->tagged_addr_enable =3D arg2 & PR_TAGGED_ADDR_ENABLE; =20 if (cpu_isar_feature(aa64_mte, cpu)) { - /* - * Write PR_MTE_TCF to SCTLR_EL1[TCF0]. - * - * The kernel has a per-cpu configuration for the sysadmin, - * /sys/devices/system/cpu/cpu/mte_tcf_preferred, - * which qemu does not implement. - * - * Because there is no performance difference between the modes, a= nd - * because SYNC is most useful for debugging MTE errors, choose SY= NC - * as the preferred mode. With this preference, and the way the A= PI - * uses only two bits, there is no way for the program to select - * ASYMM mode. - */ - unsigned tcf =3D 0; - if (arg2 & PR_MTE_TCF_SYNC) { - tcf =3D 1; - } else if (arg2 & PR_MTE_TCF_ASYNC) { - tcf =3D 2; - } - env->cp15.sctlr_el[1] =3D deposit64(env->cp15.sctlr_el[1], 38, 2, = tcf); + arm_set_mte_tcf0(env, arg2); =20 /* * Write PR_MTE_TAG to GCR_EL1[Exclude]. diff --git a/linux-user/aarch64/mte_user_helper.c b/linux-user/aarch64/mte_= user_helper.c new file mode 100644 index 0000000000..a5b1c8503b --- /dev/null +++ b/linux-user/aarch64/mte_user_helper.c @@ -0,0 +1,35 @@ +/* + * ARM MemTag convenience functions. + * + * This code is licensed under the GNU GPL v2 or later. + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ + +#include "qemu/osdep.h" +#include "qemu.h" +#include "mte_user_helper.h" + +void arm_set_mte_tcf0(CPUArchState *env, abi_long value) +{ + /* + * Write PR_MTE_TCF to SCTLR_EL1[TCF0]. + * + * The kernel has a per-cpu configuration for the sysadmin, + * /sys/devices/system/cpu/cpu/mte_tcf_preferred, + * which qemu does not implement. + * + * Because there is no performance difference between the modes, and + * because SYNC is most useful for debugging MTE errors, choose SYNC + * as the preferred mode. With this preference, and the way the API + * uses only two bits, there is no way for the program to select + * ASYMM mode. + */ + unsigned tcf =3D 0; + if (value & PR_MTE_TCF_SYNC) { + tcf =3D 1; + } else if (value & PR_MTE_TCF_ASYNC) { + tcf =3D 2; + } + env->cp15.sctlr_el[1] =3D deposit64(env->cp15.sctlr_el[1], 38, 2, tcf); +} diff --git a/linux-user/syscall.c b/linux-user/syscall.c index e2804312fc..b8c278b91d 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -6281,15 +6281,6 @@ abi_long do_arch_prctl(CPUX86State *env, int code, a= bi_ulong addr) # define PR_GET_TAGGED_ADDR_CTRL 56 # define PR_TAGGED_ADDR_ENABLE (1UL << 0) #endif -#ifndef PR_MTE_TCF_SHIFT -# define PR_MTE_TCF_SHIFT 1 -# define PR_MTE_TCF_NONE (0UL << PR_MTE_TCF_SHIFT) -# define PR_MTE_TCF_SYNC (1UL << PR_MTE_TCF_SHIFT) -# define PR_MTE_TCF_ASYNC (2UL << PR_MTE_TCF_SHIFT) -# define PR_MTE_TCF_MASK (3UL << PR_MTE_TCF_SHIFT) -# define PR_MTE_TAG_SHIFT 3 -# define PR_MTE_TAG_MASK (0xffffUL << PR_MTE_TAG_SHIFT) -#endif #ifndef PR_SET_IO_FLUSHER # define PR_SET_IO_FLUSHER 57 # define PR_GET_IO_FLUSHER 58 diff --git a/linux-user/aarch64/meson.build b/linux-user/aarch64/meson.build index 248c578d15..f75bb3cd75 100644 --- a/linux-user/aarch64/meson.build +++ b/linux-user/aarch64/meson.build @@ -9,3 +9,5 @@ vdso_le_inc =3D gen_vdso.process('vdso-le.so', extra_args: ['-r', '__kernel_rt_sigreturn']) =20 linux_user_ss.add(when: 'TARGET_AARCH64', if_true: [vdso_be_inc, vdso_le_i= nc]) + +linux_user_ss.add(when: 'TARGET_AARCH64', if_true: [files('mte_user_helper= .c')]) --=20 2.39.2