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Fri, 05 Jul 2024 01:41:11 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: Wainer dos Santos Moschetta , Beraldo Leal , David Hildenbrand , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Pierrick Bouvier , Alexandre Iooss , Thomas Huth , Mahmoud Mandour , Peter Maydell , qemu-arm@nongnu.org, Aleksandar Rikalo , Mads Ynddal , Yanan Wang , Eduardo Habkost , Peter Xu , Richard Henderson , Marcel Apfelbaum , Paul Burton , Stefan Hajnoczi , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Laurent Vivier , Gustavo Romero Subject: [PATCH v2 39/40] gdbstub: Add support for MTE in user mode Date: Fri, 5 Jul 2024 09:40:46 +0100 Message-Id: <20240705084047.857176-40-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240705084047.857176-1-alex.bennee@linaro.org> References: <20240705084047.857176-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::52f; envelope-from=alex.bennee@linaro.org; helo=mail-ed1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1720169133373100006 From: Gustavo Romero This commit implements the stubs to handle the qIsAddressTagged, qMemTag, and QMemTag GDB packets, allowing all GDB 'memory-tag' subcommands to work with QEMU gdbstub on aarch64 user mode. It also implements the get/set functions for the special GDB MTE register 'tag_ctl', used to control the MTE fault type at runtime. Signed-off-by: Gustavo Romero Signed-off-by: Alex Benn=C3=A9e Message-Id: <20240628050850.536447-11-gustavo.romero@linaro.org> --- configs/targets/aarch64-linux-user.mak | 2 +- target/arm/internals.h | 6 + target/arm/cpu.c | 1 + target/arm/gdbstub.c | 46 +++++ target/arm/gdbstub64.c | 223 +++++++++++++++++++++++++ gdb-xml/aarch64-mte.xml | 11 ++ 6 files changed, 288 insertions(+), 1 deletion(-) create mode 100644 gdb-xml/aarch64-mte.xml diff --git a/configs/targets/aarch64-linux-user.mak b/configs/targets/aarch= 64-linux-user.mak index ba8bc5fe3f..8f0ed21d76 100644 --- a/configs/targets/aarch64-linux-user.mak +++ b/configs/targets/aarch64-linux-user.mak @@ -1,6 +1,6 @@ TARGET_ARCH=3Daarch64 TARGET_BASE_ARCH=3Darm -TARGET_XML_FILES=3D gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-x= ml/aarch64-pauth.xml +TARGET_XML_FILES=3D gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-x= ml/aarch64-pauth.xml gdb-xml/aarch64-mte.xml TARGET_HAS_BFLT=3Dy CONFIG_SEMIHOSTING=3Dy CONFIG_ARM_COMPATIBLE_SEMIHOSTING=3Dy diff --git a/target/arm/internals.h b/target/arm/internals.h index 11b5da2562..e1aa1a63b9 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -358,6 +358,10 @@ void init_cpreg_list(ARMCPU *cpu); void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu); void arm_translate_init(void); =20 +void arm_cpu_register_gdb_commands(ARMCPU *cpu); +void aarch64_cpu_register_gdb_commands(ARMCPU *cpu, GString *, GArray *, + GArray *); + void arm_restore_state_to_opc(CPUState *cs, const TranslationBlock *tb, const uint64_t *data); @@ -1640,6 +1644,8 @@ int aarch64_gdb_get_fpu_reg(CPUState *cs, GByteArray = *buf, int reg); int aarch64_gdb_set_fpu_reg(CPUState *cs, uint8_t *buf, int reg); int aarch64_gdb_get_pauth_reg(CPUState *cs, GByteArray *buf, int reg); int aarch64_gdb_set_pauth_reg(CPUState *cs, uint8_t *buf, int reg); +int aarch64_gdb_get_tag_ctl_reg(CPUState *cs, GByteArray *buf, int reg); +int aarch64_gdb_set_tag_ctl_reg(CPUState *cs, uint8_t *buf, int reg); void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp); void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp); void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp); diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 35fa281f1b..14d4eca127 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2518,6 +2518,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) =20 register_cp_regs_for_features(cpu); arm_cpu_register_gdb_regs_for_features(cpu); + arm_cpu_register_gdb_commands(cpu); =20 init_cpreg_list(cpu); =20 diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index a3bb73cfa7..c3a9b5eb1e 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -21,6 +21,7 @@ #include "cpu.h" #include "exec/gdbstub.h" #include "gdbstub/helpers.h" +#include "gdbstub/commands.h" #include "sysemu/tcg.h" #include "internals.h" #include "cpu-features.h" @@ -474,6 +475,41 @@ static GDBFeature *arm_gen_dynamic_m_secextreg_feature= (CPUState *cs, #endif #endif /* CONFIG_TCG */ =20 +void arm_cpu_register_gdb_commands(ARMCPU *cpu) +{ + GArray *query_table =3D + g_array_new(FALSE, FALSE, sizeof(GdbCmdParseEntry)); + GArray *set_table =3D + g_array_new(FALSE, FALSE, sizeof(GdbCmdParseEntry)); + GString *qsupported_features =3D g_string_new(NULL); + + if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { + #ifdef TARGET_AARCH64 + aarch64_cpu_register_gdb_commands(cpu, qsupported_features, query_= table, + set_table); + #endif + } + + /* Set arch-specific handlers for 'q' commands. */ + if (query_table->len) { + gdb_extend_query_table(&g_array_index(query_table, + GdbCmdParseEntry, 0), + query_table->len); + } + + /* Set arch-specific handlers for 'Q' commands. */ + if (set_table->len) { + gdb_extend_set_table(&g_array_index(set_table, + GdbCmdParseEntry, 0), + set_table->len); + } + + /* Set arch-specific qSupported feature. */ + if (qsupported_features->len) { + gdb_extend_qsupported_features(qsupported_features->str); + } +} + void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) { CPUState *cs =3D CPU(cpu); @@ -507,6 +543,16 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cp= u) gdb_find_static_feature("aarch64-paut= h.xml"), 0); } + +#ifdef CONFIG_USER_ONLY + /* Memory Tagging Extension (MTE) 'tag_ctl' pseudo-register. */ + if (cpu_isar_feature(aa64_mte, cpu)) { + gdb_register_coprocessor(cs, aarch64_gdb_get_tag_ctl_reg, + aarch64_gdb_set_tag_ctl_reg, + gdb_find_static_feature("aarch64-mte.= xml"), + 0); + } +#endif #endif } else { if (arm_feature(env, ARM_FEATURE_NEON)) { diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c index caa31ff3fa..2e2bc2700b 100644 --- a/target/arm/gdbstub64.c +++ b/target/arm/gdbstub64.c @@ -21,6 +21,12 @@ #include "cpu.h" #include "internals.h" #include "gdbstub/helpers.h" +#include "gdbstub/commands.h" +#include "tcg/mte_helper.h" +#if defined(CONFIG_USER_ONLY) && defined(CONFIG_LINUX) +#include +#include "mte_user_helper.h" +#endif =20 int aarch64_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { @@ -381,3 +387,220 @@ GDBFeature *arm_gen_dynamic_svereg_feature(CPUState *= cs, int base_reg) =20 return &cpu->dyn_svereg_feature.desc; } + +#ifdef CONFIG_USER_ONLY +int aarch64_gdb_get_tag_ctl_reg(CPUState *cs, GByteArray *buf, int reg) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + uint64_t tcf0; + + assert(reg =3D=3D 0); + + tcf0 =3D extract64(env->cp15.sctlr_el[1], 38, 2); + + return gdb_get_reg64(buf, tcf0); +} + +int aarch64_gdb_set_tag_ctl_reg(CPUState *cs, uint8_t *buf, int reg) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + + uint8_t tcf; + + assert(reg =3D=3D 0); + + tcf =3D *buf << PR_MTE_TCF_SHIFT; + + if (!tcf) { + return 0; + } + + /* + * 'tag_ctl' register is actually a "pseudo-register" provided by GDB = to + * expose options regarding the type of MTE fault that can be controll= ed at + * runtime. + */ + arm_set_mte_tcf0(env, tcf); + + return 1; +} + +static void handle_q_memtag(GArray *params, void *user_ctx) +{ + ARMCPU *cpu =3D ARM_CPU(user_ctx); + CPUARMState *env =3D &cpu->env; + + uint64_t addr =3D gdb_get_cmd_param(params, 0)->val_ull; + uint64_t len =3D gdb_get_cmd_param(params, 1)->val_ul; + int type =3D gdb_get_cmd_param(params, 2)->val_ul; + + uint8_t *tags; + uint8_t addr_tag; + + g_autoptr(GString) str_buf =3D g_string_new(NULL); + + /* + * GDB does not query multiple tags for a memory range on remote targe= ts, so + * that's not supported either by gdbstub. + */ + if (len !=3D 1) { + gdb_put_packet("E02"); + } + + /* GDB never queries a tag different from an allocation tag (type 1). = */ + if (type !=3D 1) { + gdb_put_packet("E03"); + } + + /* Note that tags are packed here (2 tags packed in one byte). */ + tags =3D allocation_tag_mem_probe(env, 0, addr, MMU_DATA_LOAD, 8 /* 64= -bit */, + MMU_DATA_LOAD, true, 0); + if (!tags) { + /* Address is not in a tagged region. */ + gdb_put_packet("E04"); + return; + } + + /* Unpack tag from byte. */ + addr_tag =3D load_tag1(addr, tags); + g_string_printf(str_buf, "m%.2x", addr_tag); + + gdb_put_packet(str_buf->str); +} + +static void handle_q_isaddresstagged(GArray *params, void *user_ctx) +{ + ARMCPU *cpu =3D ARM_CPU(user_ctx); + CPUARMState *env =3D &cpu->env; + + uint64_t addr =3D gdb_get_cmd_param(params, 0)->val_ull; + + uint8_t *tags; + const char *reply; + + tags =3D allocation_tag_mem_probe(env, 0, addr, MMU_DATA_LOAD, 8 /* 64= -bit */, + MMU_DATA_LOAD, true, 0); + reply =3D tags ? "01" : "00"; + + gdb_put_packet(reply); +} + +static void handle_Q_memtag(GArray *params, void *user_ctx) +{ + ARMCPU *cpu =3D ARM_CPU(user_ctx); + CPUARMState *env =3D &cpu->env; + + uint64_t start_addr =3D gdb_get_cmd_param(params, 0)->val_ull; + uint64_t len =3D gdb_get_cmd_param(params, 1)->val_ul; + int type =3D gdb_get_cmd_param(params, 2)->val_ul; + char const *new_tags_str =3D gdb_get_cmd_param(params, 3)->data; + + uint64_t end_addr; + + int num_new_tags; + uint8_t *tags; + + g_autoptr(GByteArray) new_tags =3D g_byte_array_new(); + + /* + * Only the allocation tag (i.e. type 1) can be set at the stub side. + */ + if (type !=3D 1) { + gdb_put_packet("E02"); + return; + } + + end_addr =3D start_addr + (len - 1); /* 'len' is always >=3D 1 */ + /* Check if request's memory range does not cross page boundaries. */ + if ((start_addr ^ end_addr) & TARGET_PAGE_MASK) { + gdb_put_packet("E03"); + return; + } + + /* + * Get all tags in the page starting from the tag of the start address. + * Note that there are two tags packed into a single byte here. + */ + tags =3D allocation_tag_mem_probe(env, 0, start_addr, MMU_DATA_STORE, + 8 /* 64-bit */, MMU_DATA_STORE, true, = 0); + if (!tags) { + /* Address is not in a tagged region. */ + gdb_put_packet("E04"); + return; + } + + /* Convert tags provided by GDB, 2 hex digits per tag. */ + num_new_tags =3D strlen(new_tags_str) / 2; + gdb_hextomem(new_tags, new_tags_str, num_new_tags); + + uint64_t address =3D start_addr; + int new_tag_index =3D 0; + while (address <=3D end_addr) { + uint8_t new_tag; + int packed_index; + + /* + * Find packed tag index from unpacked tag index. There are two ta= gs + * in one packed index (one tag per nibble). + */ + packed_index =3D new_tag_index / 2; + + new_tag =3D new_tags->data[new_tag_index % num_new_tags]; + store_tag1(address, tags + packed_index, new_tag); + + address +=3D TAG_GRANULE; + new_tag_index++; + } + + gdb_put_packet("OK"); +} + +enum Command { + qMemTags, + qIsAddressTagged, + QMemTags, + NUM_CMDS +}; + +static GdbCmdParseEntry cmd_handler_table[NUM_CMDS] =3D { + [qMemTags] =3D { + .handler =3D handle_q_memtag, + .cmd_startswith =3D true, + .cmd =3D "MemTags:", + .schema =3D "L,l:l0", + .need_cpu_context =3D true + }, + [qIsAddressTagged] =3D { + .handler =3D handle_q_isaddresstagged, + .cmd_startswith =3D true, + .cmd =3D "IsAddressTagged:", + .schema =3D "L0", + .need_cpu_context =3D true + }, + [QMemTags] =3D { + .handler =3D handle_Q_memtag, + .cmd_startswith =3D true, + .cmd =3D "MemTags:", + .schema =3D "L,l:l:s0", + .need_cpu_context =3D true + }, +}; +#endif /* CONFIG_USER_ONLY */ + +void aarch64_cpu_register_gdb_commands(ARMCPU *cpu, GString *qsupported, + GArray *qtable, GArray *stable) +{ +#ifdef CONFIG_USER_ONLY + /* MTE */ + if (cpu_isar_feature(aa64_mte, cpu)) { + g_string_append(qsupported, ";memory-tagging+"); + + g_array_append_val(qtable, cmd_handler_table[qMemTags]); + g_array_append_val(qtable, cmd_handler_table[qIsAddressTagged]); + + g_array_append_val(stable, cmd_handler_table[QMemTags]); + } +#endif +} diff --git a/gdb-xml/aarch64-mte.xml b/gdb-xml/aarch64-mte.xml new file mode 100644 index 0000000000..4b70b4f17a --- /dev/null +++ b/gdb-xml/aarch64-mte.xml @@ -0,0 +1,11 @@ + + + + + + + --=20 2.39.2