From nobody Thu Sep 19 01:36:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1720169413; cv=none; d=zohomail.com; s=zohoarc; b=NX7VscREfTDPQuhdReG2wHazwrz0nYhZekHIA6Eto49x8U8xxZOOIjaD2oCl4OLNknX4pBDlYs+SPO8RWlxspFEZmjeMY3mESygk4tWsAN2p3AaZe6Uyja824tEYqpbgAWPr2kQH30I5KqUhg7Qnj4MXsbrq74nf1XmW5GVVlm0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1720169413; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=hQv+Mlkm0fENnTpRztWa6cDoMD7HcYttxyaEWM0xMk0=; b=EO+0tnRf7GuZ4i5gnw38Y092TIl0csqJg9EF7haX68hMeASWRMlhRHOlGyBLfmGNRdGCDvB8Uh2Wp900VVI646ZusDlNQbb5JMrfoMSAcj1Q/NWQemxEL0rdgEP6SGEakAbiSXu/H9he1XdfWmKD9sL4ML6BxuuXKc0y/60CGG8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1720169413350160.04372741966336; Fri, 5 Jul 2024 01:50:13 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sPec3-00023z-HC; Fri, 05 Jul 2024 04:48:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sPebI-0000vD-Qi for qemu-devel@nongnu.org; Fri, 05 Jul 2024 04:47:30 -0400 Received: from mail-ej1-x630.google.com ([2a00:1450:4864:20::630]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sPeb5-0004AZ-AM for qemu-devel@nongnu.org; Fri, 05 Jul 2024 04:47:27 -0400 Received: by mail-ej1-x630.google.com with SMTP id a640c23a62f3a-a77c349bb81so89549866b.3 for ; Fri, 05 Jul 2024 01:47:12 -0700 (PDT) Received: from draig.lan ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a72ab08cfc1sm661124466b.163.2024.07.05.01.47.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Jul 2024 01:47:10 -0700 (PDT) Received: from draig.lan (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id 0831062174; Fri, 5 Jul 2024 09:40:51 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1720169231; x=1720774031; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=hQv+Mlkm0fENnTpRztWa6cDoMD7HcYttxyaEWM0xMk0=; b=G2X+oM2F4JrYOPziRcA0dH3fs6hmY4YsmgYCankKw+f0WBvEXWGmstYrM+uGc4Ft5c Oc/CjzsSQO3r2l0DDIkskA9o0m00TT5cyckVqp8+l8PsfkUZZH8da9d/zh1RE32YgrHQ d8GE+FTY4nZUwFCwyCizkuAA+qcMxQb+d31PTLt52UPvfMbZuTggxVtMFy5CnXjFSTTC pqCGpjxb5+8pdKSmn1bXdIY/go0qbEZX40w9LBLzOVj/WdayVscG8CV66IXusTDQMt4e +zOmMMynWzG3F9LY+BR7KuvMdo9UaUbE9kawZDdCPJt/S+HddZpzBHknWJBJFDOns5Or zpdg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1720169231; x=1720774031; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hQv+Mlkm0fENnTpRztWa6cDoMD7HcYttxyaEWM0xMk0=; b=KNK2ZWHaUi2L4Kb2cDgR2tm79qKhMkI3GBWCvHo2RkgD7XBK72wLZG3rRRoWR9CKsJ pVJmr6QiN74IrTaSqgjxbmNjK3AyNrKpOq8RUiDaSNNDc/9zVDBPP+HtXr4qUjhKcmfn mIdgOrK5ksu1z8O6AMc1ijON6PBEd8EvVVzMt6Pm+z4x+CR2hd5EC1Y6rmAP8j4s5LLj 9SPy6ZR13QDPpLV0+NAvyX1QsEw2VDY7WEpj/j3nMwK32qxy/pBUDzPVg/t+HbXe5xFW vl6oWQM6Vt6/lHP9Apl5WDMj0leI2g+a2CtpQMrFsAqW88cW1a0F/h+bzl6RtXTncBLG 3RNA== X-Gm-Message-State: AOJu0YymBucBwFDBEakOOH9D3ljgjh0oSmBDyYKb1IG7gvwsiDavL/Ss nI9kQm1d7YGsZ66Hn+ALYOVc4QoXRlt+L+oPeSjrH5p0CG/F8vwOPj0R8v7dX0g= X-Google-Smtp-Source: AGHT+IFvD5yZrNmnbPSMFZPj5+KUonTUp7w/h/VQHX4Vm2CQ96i7C8IO4Wi8s7IOaCmyzr19iL8V0Q== X-Received: by 2002:a17:907:6e8d:b0:a77:b788:d760 with SMTP id a640c23a62f3a-a77ba72c299mr291211566b.76.1720169231163; Fri, 05 Jul 2024 01:47:11 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: Wainer dos Santos Moschetta , Beraldo Leal , David Hildenbrand , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Pierrick Bouvier , Alexandre Iooss , Thomas Huth , Mahmoud Mandour , Peter Maydell , qemu-arm@nongnu.org, Aleksandar Rikalo , Mads Ynddal , Yanan Wang , Eduardo Habkost , Peter Xu , Richard Henderson , Marcel Apfelbaum , Paul Burton , Stefan Hajnoczi , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Laurent Vivier , Gustavo Romero Subject: [PATCH v2 34/40] target/arm: Make some MTE helpers widely available Date: Fri, 5 Jul 2024 09:40:41 +0100 Message-Id: <20240705084047.857176-35-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240705084047.857176-1-alex.bennee@linaro.org> References: <20240705084047.857176-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::630; envelope-from=alex.bennee@linaro.org; helo=mail-ej1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1720169414550100001 From: Gustavo Romero Make the MTE helpers allocation_tag_mem_probe, load_tag1, and store_tag1 available to other subsystems. Signed-off-by: Gustavo Romero Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Alex Benn=C3=A9e Message-Id: <20240628050850.536447-6-gustavo.romero@linaro.org> --- target/arm/tcg/mte_helper.h | 66 +++++++++++++++++++++++++++++++++++++ target/arm/tcg/mte_helper.c | 45 ++++--------------------- 2 files changed, 73 insertions(+), 38 deletions(-) create mode 100644 target/arm/tcg/mte_helper.h diff --git a/target/arm/tcg/mte_helper.h b/target/arm/tcg/mte_helper.h new file mode 100644 index 0000000000..1f471fb69b --- /dev/null +++ b/target/arm/tcg/mte_helper.h @@ -0,0 +1,66 @@ +/* + * ARM MemTag operation helpers. + * + * This code is licensed under the GNU GPL v2 or later. + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ + +#ifndef TARGET_ARM_MTE_H +#define TARGET_ARM_MTE_H + +#include "exec/mmu-access-type.h" + +/** + * allocation_tag_mem_probe: + * @env: the cpu environment + * @ptr_mmu_idx: the addressing regime to use for the virtual address + * @ptr: the virtual address for which to look up tag memory + * @ptr_access: the access to use for the virtual address + * @ptr_size: the number of bytes in the normal memory access + * @tag_access: the access to use for the tag memory + * @probe: true to merely probe, never taking an exception + * @ra: the return address for exception handling + * + * Our tag memory is formatted as a sequence of little-endian nibbles. + * That is, the byte at (addr >> (LOG2_TAG_GRANULE + 1)) contains two + * tags, with the tag at [3:0] for the lower addr and the tag at [7:4] + * for the higher addr. + * + * Here, resolve the physical address from the virtual address, and return + * a pointer to the corresponding tag byte. + * + * If there is no tag storage corresponding to @ptr, return NULL. + * + * If the page is inaccessible for @ptr_access, or has a watchpoint, there= are + * three options: + * (1) probe =3D true, ra =3D 0 : pure probe -- we return NULL if the page= is not + * accessible, and do not take watchpoint traps. The calling code must + * handle those cases in the right priority compared to MTE traps. + * (2) probe =3D false, ra =3D 0 : probe, no fault expected -- the caller = guarantees + * that the page is going to be accessible. We will take watchpoint tr= aps. + * (3) probe =3D false, ra !=3D 0 : non-probe -- we will take both memory = access + * traps and watchpoint traps. + * (probe =3D true, ra !=3D 0 is invalid and will assert.) + */ +uint8_t *allocation_tag_mem_probe(CPUARMState *env, int ptr_mmu_idx, + uint64_t ptr, MMUAccessType ptr_access, + int ptr_size, MMUAccessType tag_access, + bool probe, uintptr_t ra); + +/** + * load_tag1 - Load 1 tag (nibble) from byte + * @ptr: The tagged address + * @mem: The tag address (packed, 2 tags in byte) + */ +int load_tag1(uint64_t ptr, uint8_t *mem); + +/** + * store_tag1 - Store 1 tag (nibble) into byte + * @ptr: The tagged address + * @mem: The tag address (packed, 2 tags in byte) + * @tag: The tag to be stored in the nibble + */ +void store_tag1(uint64_t ptr, uint8_t *mem, int tag); + +#endif /* TARGET_ARM_MTE_H */ diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c index a50d576294..9d2ba287ee 100644 --- a/target/arm/tcg/mte_helper.c +++ b/target/arm/tcg/mte_helper.c @@ -29,6 +29,7 @@ #include "hw/core/tcg-cpu-ops.h" #include "qapi/error.h" #include "qemu/guest-random.h" +#include "mte_helper.h" =20 =20 static int choose_nonexcluded_tag(int tag, int offset, uint16_t exclude) @@ -50,42 +51,10 @@ static int choose_nonexcluded_tag(int tag, int offset, = uint16_t exclude) return tag; } =20 -/** - * allocation_tag_mem_probe: - * @env: the cpu environment - * @ptr_mmu_idx: the addressing regime to use for the virtual address - * @ptr: the virtual address for which to look up tag memory - * @ptr_access: the access to use for the virtual address - * @ptr_size: the number of bytes in the normal memory access - * @tag_access: the access to use for the tag memory - * @probe: true to merely probe, never taking an exception - * @ra: the return address for exception handling - * - * Our tag memory is formatted as a sequence of little-endian nibbles. - * That is, the byte at (addr >> (LOG2_TAG_GRANULE + 1)) contains two - * tags, with the tag at [3:0] for the lower addr and the tag at [7:4] - * for the higher addr. - * - * Here, resolve the physical address from the virtual address, and return - * a pointer to the corresponding tag byte. - * - * If there is no tag storage corresponding to @ptr, return NULL. - * - * If the page is inaccessible for @ptr_access, or has a watchpoint, there= are - * three options: - * (1) probe =3D true, ra =3D 0 : pure probe -- we return NULL if the page= is not - * accessible, and do not take watchpoint traps. The calling code must - * handle those cases in the right priority compared to MTE traps. - * (2) probe =3D false, ra =3D 0 : probe, no fault expected -- the caller = guarantees - * that the page is going to be accessible. We will take watchpoint tr= aps. - * (3) probe =3D false, ra !=3D 0 : non-probe -- we will take both memory = access - * traps and watchpoint traps. - * (probe =3D true, ra !=3D 0 is invalid and will assert.) - */ -static uint8_t *allocation_tag_mem_probe(CPUARMState *env, int ptr_mmu_idx, - uint64_t ptr, MMUAccessType ptr_a= ccess, - int ptr_size, MMUAccessType tag_a= ccess, - bool probe, uintptr_t ra) +uint8_t *allocation_tag_mem_probe(CPUARMState *env, int ptr_mmu_idx, + uint64_t ptr, MMUAccessType ptr_access, + int ptr_size, MMUAccessType tag_access, + bool probe, uintptr_t ra) { #ifdef CONFIG_USER_ONLY uint64_t clean_ptr =3D useronly_clean_ptr(ptr); @@ -287,7 +256,7 @@ uint64_t HELPER(addsubg)(CPUARMState *env, uint64_t ptr, return address_with_allocation_tag(ptr + offset, rtag); } =20 -static int load_tag1(uint64_t ptr, uint8_t *mem) +int load_tag1(uint64_t ptr, uint8_t *mem) { int ofs =3D extract32(ptr, LOG2_TAG_GRANULE, 1) * 4; return extract32(*mem, ofs, 4); @@ -321,7 +290,7 @@ static void check_tag_aligned(CPUARMState *env, uint64_= t ptr, uintptr_t ra) } =20 /* For use in a non-parallel context, store to the given nibble. */ -static void store_tag1(uint64_t ptr, uint8_t *mem, int tag) +void store_tag1(uint64_t ptr, uint8_t *mem, int tag) { int ofs =3D extract32(ptr, LOG2_TAG_GRANULE, 1) * 4; *mem =3D deposit32(*mem, ofs, 4, tag); --=20 2.39.2