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Tsirkin" , Bernhard Beschow Subject: [PATCH 1/3] hw/isa/vt82c686: Turn "intr" irq into a named gpio Date: Thu, 4 Jul 2024 22:58:52 +0200 Message-ID: <20240704205854.18537-2-shentey@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240704205854.18537-1-shentey@gmail.com> References: <20240704205854.18537-1-shentey@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::532; envelope-from=shentey@gmail.com; helo=mail-ed1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1720126822403100001 Content-Type: text/plain; charset="utf-8" Makes the code more comprehensible, matches the datasheet and the piix4 dev= ice model. Signed-off-by: Bernhard Beschow Reviewed-by: BALATON Zoltan Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/isa/vt82c686.c | 2 +- hw/mips/fuloong2e.c | 2 +- hw/ppc/amigaone.c | 4 ++-- hw/ppc/pegasos2.c | 4 ++-- 4 files changed, 6 insertions(+), 6 deletions(-) diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c index 8582ac0322..505b44c4e6 100644 --- a/hw/isa/vt82c686.c +++ b/hw/isa/vt82c686.c @@ -719,7 +719,7 @@ static void via_isa_realize(PCIDevice *d, Error **errp) ISABus *isa_bus; int i; =20 - qdev_init_gpio_out(dev, &s->cpu_intr, 1); + qdev_init_gpio_out_named(dev, &s->cpu_intr, "intr", 1); qdev_init_gpio_in_named(dev, via_isa_pirq, "pirq", PCI_NUM_PINS); isa_irq =3D qemu_allocate_irqs(via_isa_request_i8259_irq, s, 1); isa_bus =3D isa_bus_new(dev, pci_address_space(d), pci_address_space_i= o(d), diff --git a/hw/mips/fuloong2e.c b/hw/mips/fuloong2e.c index a45aac368c..6e4303ba47 100644 --- a/hw/mips/fuloong2e.c +++ b/hw/mips/fuloong2e.c @@ -299,7 +299,7 @@ static void mips_fuloong2e_init(MachineState *machine) object_resolve_path_component(OBJECT(pci_dev= ), "rtc"), "date"); - qdev_connect_gpio_out(DEVICE(pci_dev), 0, env->irq[5]); + qdev_connect_gpio_out_named(DEVICE(pci_dev), "intr", 0, env->irq[5]); =20 dev =3D DEVICE(object_resolve_path_component(OBJECT(pci_dev), "ide")); pci_ide_create_devs(PCI_DEVICE(dev)); diff --git a/hw/ppc/amigaone.c b/hw/ppc/amigaone.c index ddfa09457a..9dcc486c1a 100644 --- a/hw/ppc/amigaone.c +++ b/hw/ppc/amigaone.c @@ -153,8 +153,8 @@ static void amigaone_init(MachineState *machine) object_property_add_alias(OBJECT(machine), "rtc-time", object_resolve_path_component(via, "rtc"), "date"); - qdev_connect_gpio_out(DEVICE(via), 0, - qdev_get_gpio_in(DEVICE(cpu), PPC6xx_INPUT_INT)); + qdev_connect_gpio_out_named(DEVICE(via), "intr", 0, + qdev_get_gpio_in(DEVICE(cpu), PPC6xx_INPUT= _INT)); for (i =3D 0; i < PCI_NUM_PINS; i++) { qdev_connect_gpio_out(dev, i, qdev_get_gpio_in_named(DEVICE(via), "pirq", i)); diff --git a/hw/ppc/pegasos2.c b/hw/ppc/pegasos2.c index c1bd8dfa21..9b0a6b70ab 100644 --- a/hw/ppc/pegasos2.c +++ b/hw/ppc/pegasos2.c @@ -195,8 +195,8 @@ static void pegasos2_init(MachineState *machine) object_property_add_alias(OBJECT(machine), "rtc-time", object_resolve_path_component(via, "rtc"), "date"); - qdev_connect_gpio_out(DEVICE(via), 0, - qdev_get_gpio_in_named(pm->mv, "gpp", 31)); + qdev_connect_gpio_out_named(DEVICE(via), "intr", 0, + qdev_get_gpio_in_named(pm->mv, "gpp", 31)); =20 dev =3D PCI_DEVICE(object_resolve_path_component(via, "ide")); pci_ide_create_devs(dev); --=20 2.45.2 From nobody Sun Nov 24 21:41:12 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1720126821; cv=none; d=zohomail.com; s=zohoarc; b=cTJkzIplaHpXJrdVa/H1J7oNpvlfe/5dm29fXN/t8FNpBsulK0u+IMAvmThjPIbaoRvNeejXKfe5XhoKx/1R01Ekzm+BPQpJZJDtpCs71vDqTRUTQJ3QTZ8GTIQNv0BXOhZbb7fTTe6urghzpeaHdKmVylwHJUX7GvJ3Y/iVhtk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1720126821; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=oWtJCgARShGh4Hv3ul6ITFwgpH0VxBhfZ7ANN/LEg44=; b=kQmCBhAfYTYT7GCnRYNc+sdIuEzPOzQxD1YKQbi564NHS/OjZ6m0C9H7H8XBpb4gEA/MU5X+AYTEPSL3pV+TSTjtXe7KFOwMLO9+cYLIWnI+3MRfyAZKUn47PeT3GXMClz5XdVf8plpgqzxqhiYZ0KoBZ8JCHi+g/i2R7e2xV+g= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1720126821330872.1003129110209; Thu, 4 Jul 2024 14:00:21 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sPTY5-0003BI-BC; Thu, 04 Jul 2024 16:59:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sPTY0-00038a-MQ; Thu, 04 Jul 2024 16:59:21 -0400 Received: from mail-ej1-x62c.google.com ([2a00:1450:4864:20::62c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sPTXy-0000nk-Uc; Thu, 04 Jul 2024 16:59:20 -0400 Received: by mail-ej1-x62c.google.com with SMTP id a640c23a62f3a-a77b4387302so127184566b.1; Thu, 04 Jul 2024 13:59:18 -0700 (PDT) Received: from archlinux.. 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Tsirkin" , Bernhard Beschow Subject: [PATCH 2/3] hw/isa/vt82c686: Resolve intermediate IRQ forwarder Date: Thu, 4 Jul 2024 22:58:53 +0200 Message-ID: <20240704205854.18537-3-shentey@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240704205854.18537-1-shentey@gmail.com> References: <20240704205854.18537-1-shentey@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::62c; envelope-from=shentey@gmail.com; helo=mail-ej1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1720126822404100002 When @cpu_intr is populated before vt82xx's realize(), it can be directly p= assed to i8259_init(), avoiding the need for the intermediate via_isa_request_i8259_irq() handler. The result is less code and runtime overhead, and a fixed memory leak caused by qemu_allocate_irqs(). Inspired-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Bernhard Beschow --- hw/isa/vt82c686.c | 12 ++---------- hw/mips/fuloong2e.c | 2 +- hw/ppc/amigaone.c | 8 ++++---- hw/ppc/pegasos2.c | 4 ++-- 4 files changed, 9 insertions(+), 17 deletions(-) diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c index 505b44c4e6..ca02ad4c20 100644 --- a/hw/isa/vt82c686.c +++ b/hw/isa/vt82c686.c @@ -624,6 +624,7 @@ static void via_isa_init(Object *obj) object_initialize_child(obj, "uhci2", &s->uhci[1], TYPE_VT82C686B_USB_= UHCI); object_initialize_child(obj, "ac97", &s->ac97, TYPE_VIA_AC97); object_initialize_child(obj, "mc97", &s->mc97, TYPE_VIA_MC97); + qdev_init_gpio_out_named(DEVICE(obj), &s->cpu_intr, "intr", 1); } =20 static const TypeInfo via_isa_info =3D { @@ -704,24 +705,15 @@ static void via_isa_pirq(void *opaque, int pin, int l= evel) via_isa_set_irq(opaque, pin, level); } =20 -static void via_isa_request_i8259_irq(void *opaque, int irq, int level) -{ - ViaISAState *s =3D opaque; - qemu_set_irq(s->cpu_intr, level); -} - static void via_isa_realize(PCIDevice *d, Error **errp) { ViaISAState *s =3D VIA_ISA(d); DeviceState *dev =3D DEVICE(d); PCIBus *pci_bus =3D pci_get_bus(d); - qemu_irq *isa_irq; ISABus *isa_bus; int i; =20 - qdev_init_gpio_out_named(dev, &s->cpu_intr, "intr", 1); qdev_init_gpio_in_named(dev, via_isa_pirq, "pirq", PCI_NUM_PINS); - isa_irq =3D qemu_allocate_irqs(via_isa_request_i8259_irq, s, 1); isa_bus =3D isa_bus_new(dev, pci_address_space(d), pci_address_space_i= o(d), errp); =20 @@ -729,7 +721,7 @@ static void via_isa_realize(PCIDevice *d, Error **errp) return; } =20 - s->isa_irqs_in =3D i8259_init(isa_bus, *isa_irq); + s->isa_irqs_in =3D i8259_init(isa_bus, s->cpu_intr); isa_bus_register_input_irqs(isa_bus, s->isa_irqs_in); i8254_pit_init(isa_bus, 0x40, 0, NULL); i8257_dma_init(OBJECT(d), isa_bus, 0); diff --git a/hw/mips/fuloong2e.c b/hw/mips/fuloong2e.c index 6e4303ba47..e6487c34d8 100644 --- a/hw/mips/fuloong2e.c +++ b/hw/mips/fuloong2e.c @@ -286,6 +286,7 @@ static void mips_fuloong2e_init(MachineState *machine) /* South bridge -> IP5 */ pci_dev =3D pci_new_multifunction(PCI_DEVFN(FULOONG2E_VIA_SLOT, 0), TYPE_VT82C686B_ISA); + qdev_connect_gpio_out_named(DEVICE(pci_dev), "intr", 0, env->irq[5]); =20 /* Set properties on individual devices before realizing the south bri= dge */ if (machine->audiodev) { @@ -299,7 +300,6 @@ static void mips_fuloong2e_init(MachineState *machine) object_resolve_path_component(OBJECT(pci_dev= ), "rtc"), "date"); - qdev_connect_gpio_out_named(DEVICE(pci_dev), "intr", 0, env->irq[5]); =20 dev =3D DEVICE(object_resolve_path_component(OBJECT(pci_dev), "ide")); pci_ide_create_devs(PCI_DEVICE(dev)); diff --git a/hw/ppc/amigaone.c b/hw/ppc/amigaone.c index 9dcc486c1a..2110875f56 100644 --- a/hw/ppc/amigaone.c +++ b/hw/ppc/amigaone.c @@ -148,13 +148,13 @@ static void amigaone_init(MachineState *machine) pci_bus =3D PCI_BUS(qdev_get_child_bus(dev, "pci.0")); =20 /* VIA VT82c686B South Bridge (multifunction PCI device) */ - via =3D OBJECT(pci_create_simple_multifunction(pci_bus, PCI_DEVFN(7, 0= ), - TYPE_VT82C686B_ISA)); + via =3D OBJECT(pci_new_multifunction(PCI_DEVFN(7, 0), TYPE_VT82C686B_I= SA)); + qdev_connect_gpio_out_named(DEVICE(via), "intr", 0, + qdev_get_gpio_in(DEVICE(cpu), PPC6xx_INPUT= _INT)); + pci_realize_and_unref(PCI_DEVICE(via), pci_bus, &error_abort); object_property_add_alias(OBJECT(machine), "rtc-time", object_resolve_path_component(via, "rtc"), "date"); - qdev_connect_gpio_out_named(DEVICE(via), "intr", 0, - qdev_get_gpio_in(DEVICE(cpu), PPC6xx_INPUT= _INT)); for (i =3D 0; i < PCI_NUM_PINS; i++) { qdev_connect_gpio_out(dev, i, qdev_get_gpio_in_named(DEVICE(via), "pirq", i)); diff --git a/hw/ppc/pegasos2.c b/hw/ppc/pegasos2.c index 9b0a6b70ab..54e60082ce 100644 --- a/hw/ppc/pegasos2.c +++ b/hw/ppc/pegasos2.c @@ -181,6 +181,8 @@ static void pegasos2_init(MachineState *machine) =20 /* VIA VT8231 South Bridge (multifunction PCI device) */ via =3D OBJECT(pci_new_multifunction(PCI_DEVFN(12, 0), TYPE_VT8231_ISA= )); + qdev_connect_gpio_out_named(DEVICE(via), "intr", 0, + qdev_get_gpio_in_named(pm->mv, "gpp", 31)); =20 /* Set properties on individual devices before realizing the south bri= dge */ if (machine->audiodev) { @@ -195,8 +197,6 @@ static void pegasos2_init(MachineState *machine) object_property_add_alias(OBJECT(machine), "rtc-time", object_resolve_path_component(via, "rtc"), "date"); - qdev_connect_gpio_out_named(DEVICE(via), "intr", 0, - qdev_get_gpio_in_named(pm->mv, "gpp", 31)); =20 dev =3D PCI_DEVICE(object_resolve_path_component(via, "ide")); pci_ide_create_devs(dev); --=20 2.45.2 From nobody Sun Nov 24 21:41:12 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1720126831; cv=none; d=zohomail.com; s=zohoarc; b=DXDagwqeJZwim4yu0cWr9Xkux5BplTN1f2eZ6MyW0VA8NvDwgUAZZQxb30G94y42MAc1kLEZVa3FEE4UTRi8SXHg0Nh/iPsc20lZRwkNUJrt7/m2kOyc9XGwiGrWBLYOIfk+eggYwccBUbFzSeYD91n7QfN8wVpePXEowTwZfJ8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1720126831; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Tsirkin" , Bernhard Beschow Subject: [PATCH 3/3] hw/isa/piix: Resolve intermediate IRQ forwarder Date: Thu, 4 Jul 2024 22:58:54 +0200 Message-ID: <20240704205854.18537-4-shentey@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240704205854.18537-1-shentey@gmail.com> References: <20240704205854.18537-1-shentey@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::635; envelope-from=shentey@gmail.com; helo=mail-ej1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1720126831868100001 When @cpu_intr is populated before pixx4's realize(), it can be directly pa= ssed to i8259_init(), avoiding the need for the intermediate piix_request_i8259_= irq() handler. The result is less code and runtime overhead, and a fixed memory l= eak caused by qemu_allocate_irqs(). Inspired-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Bernhard Beschow --- hw/isa/piix.c | 13 ++----------- hw/mips/malta.c | 4 +--- 2 files changed, 3 insertions(+), 14 deletions(-) diff --git a/hw/isa/piix.c b/hw/isa/piix.c index 2d30711b17..e070628f25 100644 --- a/hw/isa/piix.c +++ b/hw/isa/piix.c @@ -81,12 +81,6 @@ static void piix_set_pci_irq(void *opaque, int pirq, int= level) piix_set_pci_irq_level(s, pirq, level); } =20 -static void piix_request_i8259_irq(void *opaque, int irq, int level) -{ - PIIXState *s =3D opaque; - qemu_set_irq(s->cpu_intr, level); -} - static PCIINTxRoute piix_route_intx_pin_to_irq(void *opaque, int pin) { PCIDevice *pci_dev =3D opaque; @@ -315,9 +309,7 @@ static void pci_piix_realize(PCIDevice *dev, const char= *uhci_type, =20 /* PIC */ if (d->has_pic) { - qemu_irq *i8259_out_irq =3D qemu_allocate_irqs(piix_request_i8259_= irq, d, - 1); - qemu_irq *i8259 =3D i8259_init(isa_bus, *i8259_out_irq); + qemu_irq *i8259 =3D i8259_init(isa_bus, d->cpu_intr); size_t i; =20 for (i =3D 0; i < ISA_NUM_IRQS; i++) { @@ -325,8 +317,6 @@ static void pci_piix_realize(PCIDevice *dev, const char= *uhci_type, } =20 g_free(i8259); - - qdev_init_gpio_out_named(DEVICE(dev), &d->cpu_intr, "intr", 1); } =20 isa_bus_register_input_irqs(isa_bus, d->isa_irqs_in); @@ -402,6 +392,7 @@ static void pci_piix_init(Object *obj) { PIIXState *d =3D PIIX_PCI_DEVICE(obj); =20 + qdev_init_gpio_out_named(DEVICE(obj), &d->cpu_intr, "intr", 1); qdev_init_gpio_out_named(DEVICE(obj), d->isa_irqs_in, "isa-irqs", ISA_NUM_IRQS); =20 diff --git a/hw/mips/malta.c b/hw/mips/malta.c index 664a2ae0a9..50823bd5fb 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -1238,15 +1238,13 @@ void mips_malta_init(MachineState *machine) /* Southbridge */ piix4 =3D pci_new_multifunction(PIIX4_PCI_DEVFN, TYPE_PIIX4_PCI_DEVICE= ); qdev_prop_set_uint32(DEVICE(piix4), "smb_io_base", 0x1100); + qdev_connect_gpio_out_named(DEVICE(piix4), "intr", 0, i8259_irq); pci_realize_and_unref(piix4, pci_bus, &error_fatal); isa_bus =3D ISA_BUS(qdev_get_child_bus(DEVICE(piix4), "isa.0")); =20 dev =3D DEVICE(object_resolve_path_component(OBJECT(piix4), "ide")); pci_ide_create_devs(PCI_DEVICE(dev)); =20 - /* Interrupt controller */ - qdev_connect_gpio_out_named(DEVICE(piix4), "intr", 0, i8259_irq); - /* generate SPD EEPROM data */ dev =3D DEVICE(object_resolve_path_component(OBJECT(piix4), "pm")); smbus =3D I2C_BUS(qdev_get_child_bus(dev, "i2c")); --=20 2.45.2