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Thu, 04 Jul 2024 02:58:27 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEt3D+mPlZv70+ZMY47xcWhULRk9EV/JIyeppJd5DyPT38ApverxhnbUDAD6jMIAuujdOWwPg== X-Received: by 2002:a05:600c:5349:b0:425:5e9a:5958 with SMTP id 5b1f17b1804b1-4264a3e88d1mr8492995e9.22.1720087107531; Thu, 04 Jul 2024 02:58:27 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: Xiaoyao Li , John Allen Subject: [PULL 08/16] target/i386: drop AMD machine check bits from Intel CPUID Date: Thu, 4 Jul 2024 11:57:58 +0200 Message-ID: <20240704095806.1780273-9-pbonzini@redhat.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240704095806.1780273-1-pbonzini@redhat.com> References: <20240704095806.1780273-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1720087222200100005 Content-Type: text/plain; charset="utf-8" The recent addition of the SUCCOR bit to kvm_arch_get_supported_cpuid() causes the bit to be visible when "-cpu host" VMs are started on Intel processors. While this should in principle be harmless, it's not tidy and we don't even know for sure that it doesn't cause any guest OS to take unexpected paths. Since x86_cpu_get_supported_feature_word() can return different different values depending on the guest, adjust it to hide the SUCCOR bit if the guest has non-AMD vendor. Suggested-by: Xiaoyao Li Cc: John Allen Signed-off-by: Paolo Bonzini --- target/i386/cpu.c | 23 +++++++++++++++++++---- 1 file changed, 19 insertions(+), 4 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 4364cb0f8e3..5e5bf71702c 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6039,6 +6039,7 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *c= pu, FeatureWord w) { FeatureWordInfo *wi =3D &feature_word_info[w]; uint64_t r =3D 0; + uint32_t unavail =3D 0; =20 if (kvm_enabled()) { switch (wi->type) { @@ -6064,19 +6065,33 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU = *cpu, FeatureWord w) } else { return ~0; } + + switch (w) { #ifndef TARGET_X86_64 - if (w =3D=3D FEAT_8000_0001_EDX) { + case FEAT_8000_0001_EDX: /* * 32-bit TCG can emulate 64-bit compatibility mode. If there is = no * way for userspace to get out of its 32-bit jail, we can leave * the LM bit set. */ - uint32_t unavail =3D tcg_enabled() + unavail =3D tcg_enabled() ? CPUID_EXT2_LM & ~CPUID_EXT2_KERNEL_FEATURES : CPUID_EXT2_LM; - r &=3D ~unavail; - } + break; #endif + + case FEAT_8000_0007_EBX: + if (cpu && !IS_AMD_CPU(&cpu->env)) { + /* Disable AMD machine check architecture for Intel CPU. */ + unavail =3D ~0; + } + break; + + default: + break; + } + + r &=3D ~unavail; if (cpu && cpu->migratable) { r &=3D x86_cpu_get_migratable_flags(w); } --=20 2.45.2