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Thu, 04 Jul 2024 02:58:31 -0700 (PDT) X-Google-Smtp-Source: AGHT+IH2d7pjRtK/y4tRaCePStbfdb7cFHEqio4Q9CKTU86/vYRj+HdJQeMBy9PKSnx3DzlKf/ij5g== X-Received: by 2002:a05:600c:1d01:b0:424:a823:51d7 with SMTP id 5b1f17b1804b1-4264a3d98edmr7901815e9.5.1720087111483; Thu, 04 Jul 2024 02:58:31 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Subject: [PULL 10/16] target/i386: do not include undefined bits in the AMD topoext leaf Date: Thu, 4 Jul 2024 11:58:00 +0200 Message-ID: <20240704095806.1780273-11-pbonzini@redhat.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240704095806.1780273-1-pbonzini@redhat.com> References: <20240704095806.1780273-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1720087242232100001 Content-Type: text/plain; charset="utf-8" Commit d7c72735f61 ("target/i386: Add new EPYC CPU versions with updated cache_info", 2023-05-08) ensured that AMD-defined CPU models did not have the 'complex_indexing' bit set, but left it set in "-cpu host" which uses the default ("legacy") cache information. Reimplement that commit using a CPU feature, so that it can be applied to all guests using a new machine type, independent of the CPU model. Signed-off-by: Paolo Bonzini --- target/i386/cpu.h | 3 +++ hw/i386/pc.c | 1 + target/i386/cpu.c | 4 ++++ 3 files changed, 8 insertions(+) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 9bea7142bf4..0d5624355e4 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2104,6 +2104,9 @@ struct ArchCPU { /* Only advertise CPUID leaves defined by the vendor */ bool vendor_cpuid_only; =20 + /* Only advertise TOPOEXT features that AMD defines */ + bool amd_topoext_features_only; + /* Enable auto level-increase for Intel Processor Trace leave */ bool intel_pt_auto_level; =20 diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 77415064c62..5dff91422ff 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -80,6 +80,7 @@ { "athlon-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, }, =20 GlobalProperty pc_compat_9_0[] =3D { + { TYPE_X86_CPU, "x-amd-topoext-features-only", "false" }, { TYPE_X86_CPU, "x-l1-cache-per-thread", "false" }, { TYPE_X86_CPU, "guest-phys-bits", "0" }, { "sev-guest", "legacy-vm-type", "true" }, diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 5e5bf71702c..c40551d9bfb 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6982,6 +6982,9 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, *eax =3D *ebx =3D *ecx =3D *edx =3D 0; break; } + if (cpu->amd_topoext_features_only) { + *edx &=3D CACHE_NO_INVD_SHARING | CACHE_INCLUSIVE; + } break; case 0x8000001E: if (cpu->core_id <=3D 255) { @@ -8293,6 +8296,7 @@ static Property x86_cpu_properties[] =3D { DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor), DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true), DEFINE_PROP_BOOL("x-vendor-cpuid-only", X86CPU, vendor_cpuid_only, tru= e), + DEFINE_PROP_BOOL("x-amd-topoext-features-only", X86CPU, amd_topoext_fe= atures_only, true), DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false), DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true), DEFINE_PROP_BOOL("kvm-pv-enforce-cpuid", X86CPU, kvm_pv_enforce_cpuid, --=20 2.45.2