From nobody Thu Sep 19 00:52:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1720081915; cv=none; d=zohomail.com; s=zohoarc; b=noknvWrBbxN/41+TZfEXvP9SBwM0jV5MVjb30Bmqgr8qxHke15lCKWCyVfIZ5aNkdfpwcq7gk0hGbf3zyCnW5WadZDXqNtCeIk6KQBPRERV+8gPpal2VkDxLgNcnlNqdIpLAkjFUmH7eOxO8oEraeATwA5MoRyuDrU6N4DZ6fZA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1720081915; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=VYySlEODKQfmmttNWCyDtel+LMreSsMvTCeHyAzFBBM=; b=DNyZvk3sYtWh5FDg50PtYx8N7CGLn5ovb2bL4xs2xGIw70tbK3Oq6d8wElygpijILNClNafCnc/2SJFeJBdBMMXGBqgbsBapZuc5HDi3hG5UTDn4g4pYezWYqOveWvNuM1fNyrDMH8v49Iu8eEG9BNnGluMDcF/jgvccdCEcv90= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1720081915260322.4901444003275; Thu, 4 Jul 2024 01:31:55 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sPHqe-0000SM-I1; Thu, 04 Jul 2024 04:29:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sPHqc-0000RU-5G; Thu, 04 Jul 2024 04:29:46 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sPHqW-0002HT-PL; Thu, 04 Jul 2024 04:29:45 -0400 Received: from TWMBX02.aspeed.com (192.168.0.24) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.1258.12; Thu, 4 Jul 2024 16:29:23 +0800 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX02.aspeed.com (192.168.0.25) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 4 Jul 2024 16:29:23 +0800 Received: from localhost.localdomain (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Thu, 4 Jul 2024 16:29:23 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , Alistair Francis , "Kevin Wolf" , Hanna Reitz , Jason Wang , Cleber Rosa , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Wainer dos Santos Moschetta" , Beraldo Leal , "open list:ASPEED BMCs" , "open list:All patches CC here" , "open list:Block layer core" CC: , , Subject: [PATCH v3 2/8] hw/net:ftgmac100: update ring base address to 64 bits Date: Thu, 4 Jul 2024 16:29:16 +0800 Message-ID: <20240704082922.1464317-3-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240704082922.1464317-1-jamin_lin@aspeedtech.com> References: <20240704082922.1464317-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: Fail (TWMBX02.aspeed.com: domain of jamin_lin@aspeedtech.com does not designate 192.168.10.10 as permitted sender) receiver=TWMBX02.aspeed.com; client-ip=192.168.10.10; helo=localhost.localdomain; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1720081916226100003 Content-Type: text/plain; charset="utf-8" Update TX and RX ring base address data type to uint64_t for 64 bits dram address DMA support. Both "Normal Priority Transmit Ring Base Address Register(0x20)" and "Receive Ring Base Address Register (0x24)" are used for saving the low part physical address of descriptor manager. Therefore, changes to set TX and RX descriptor manager address bits [31:0] in ftgmac100_read and ftgmac100_write functions. Incrementing the version of vmstate to 2. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater --- hw/net/ftgmac100.c | 33 ++++++++++++++++----------------- include/hw/net/ftgmac100.h | 9 ++++----- 2 files changed, 20 insertions(+), 22 deletions(-) diff --git a/hw/net/ftgmac100.c b/hw/net/ftgmac100.c index 9e1f12cd33..d026242e2b 100644 --- a/hw/net/ftgmac100.c +++ b/hw/net/ftgmac100.c @@ -515,12 +515,12 @@ out: return frame_size; } =20 -static void ftgmac100_do_tx(FTGMAC100State *s, uint32_t tx_ring, - uint32_t tx_descriptor) +static void ftgmac100_do_tx(FTGMAC100State *s, uint64_t tx_ring, + uint64_t tx_descriptor) { int frame_size =3D 0; uint8_t *ptr =3D s->frame; - uint32_t addr =3D tx_descriptor; + uint64_t addr =3D tx_descriptor; uint32_t flags =3D 0; =20 while (1) { @@ -726,9 +726,9 @@ static uint64_t ftgmac100_read(void *opaque, hwaddr add= r, unsigned size) case FTGMAC100_MATH1: return s->math[1]; case FTGMAC100_RXR_BADR: - return s->rx_ring; + return extract64(s->rx_ring, 0, 32); case FTGMAC100_NPTXR_BADR: - return s->tx_ring; + return extract64(s->tx_ring, 0, 32); case FTGMAC100_ITC: return s->itc; case FTGMAC100_DBLAC: @@ -799,9 +799,8 @@ static void ftgmac100_write(void *opaque, hwaddr addr, HWADDR_PRIx "\n", __func__, value); return; } - - s->rx_ring =3D value; - s->rx_descriptor =3D s->rx_ring; + s->rx_ring =3D deposit64(s->rx_ring, 0, 32, value); + s->rx_descriptor =3D deposit64(s->rx_descriptor, 0, 32, value); break; =20 case FTGMAC100_RBSR: /* DMA buffer size */ @@ -814,8 +813,8 @@ static void ftgmac100_write(void *opaque, hwaddr addr, HWADDR_PRIx "\n", __func__, value); return; } - s->tx_ring =3D value; - s->tx_descriptor =3D s->tx_ring; + s->tx_ring =3D deposit64(s->tx_ring, 0, 32, value); + s->tx_descriptor =3D deposit64(s->tx_descriptor, 0, 32, value); break; =20 case FTGMAC100_NPTXPD: /* Trigger transmit */ @@ -957,7 +956,7 @@ static ssize_t ftgmac100_receive(NetClientState *nc, co= nst uint8_t *buf, FTGMAC100State *s =3D FTGMAC100(qemu_get_nic_opaque(nc)); FTGMAC100Desc bd; uint32_t flags =3D 0; - uint32_t addr; + uint64_t addr; uint32_t crc; uint32_t buf_addr; uint8_t *crc_ptr; @@ -1126,18 +1125,14 @@ static void ftgmac100_realize(DeviceState *dev, Err= or **errp) =20 static const VMStateDescription vmstate_ftgmac100 =3D { .name =3D TYPE_FTGMAC100, - .version_id =3D 1, - .minimum_version_id =3D 1, + .version_id =3D 2, + .minimum_version_id =3D 2, .fields =3D (const VMStateField[]) { VMSTATE_UINT32(irq_state, FTGMAC100State), VMSTATE_UINT32(isr, FTGMAC100State), VMSTATE_UINT32(ier, FTGMAC100State), VMSTATE_UINT32(rx_enabled, FTGMAC100State), - VMSTATE_UINT32(rx_ring, FTGMAC100State), VMSTATE_UINT32(rbsr, FTGMAC100State), - VMSTATE_UINT32(tx_ring, FTGMAC100State), - VMSTATE_UINT32(rx_descriptor, FTGMAC100State), - VMSTATE_UINT32(tx_descriptor, FTGMAC100State), VMSTATE_UINT32_ARRAY(math, FTGMAC100State, 2), VMSTATE_UINT32(itc, FTGMAC100State), VMSTATE_UINT32(aptcr, FTGMAC100State), @@ -1156,6 +1151,10 @@ static const VMStateDescription vmstate_ftgmac100 = =3D { VMSTATE_UINT32(phy_int_mask, FTGMAC100State), VMSTATE_UINT32(txdes0_edotr, FTGMAC100State), VMSTATE_UINT32(rxdes0_edorr, FTGMAC100State), + VMSTATE_UINT64(rx_ring, FTGMAC100State), + VMSTATE_UINT64(tx_ring, FTGMAC100State), + VMSTATE_UINT64(rx_descriptor, FTGMAC100State), + VMSTATE_UINT64(tx_descriptor, FTGMAC100State), VMSTATE_END_OF_LIST() } }; diff --git a/include/hw/net/ftgmac100.h b/include/hw/net/ftgmac100.h index 269446e858..aae57ae8cb 100644 --- a/include/hw/net/ftgmac100.h +++ b/include/hw/net/ftgmac100.h @@ -42,10 +42,6 @@ struct FTGMAC100State { uint32_t isr; uint32_t ier; uint32_t rx_enabled; - uint32_t rx_ring; - uint32_t rx_descriptor; - uint32_t tx_ring; - uint32_t tx_descriptor; uint32_t math[2]; uint32_t rbsr; uint32_t itc; @@ -58,7 +54,10 @@ struct FTGMAC100State { uint32_t phycr; uint32_t phydata; uint32_t fcr; - + uint64_t rx_ring; + uint64_t rx_descriptor; + uint64_t tx_ring; + uint64_t tx_descriptor; =20 uint32_t phy_status; uint32_t phy_control; --=20 2.34.1