From nobody Sun Nov 24 20:41:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1720064389932430.23673186196254; Wed, 3 Jul 2024 20:39:49 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sPDIZ-0007tW-UC; Wed, 03 Jul 2024 23:38:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sPDIW-0007qy-Qf for qemu-devel@nongnu.org; Wed, 03 Jul 2024 23:38:17 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sPDIS-0003AK-P7 for qemu-devel@nongnu.org; Wed, 03 Jul 2024 23:38:16 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8Ax3vAbGYZmC80AAA--.2620S3; Thu, 04 Jul 2024 11:38:03 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by localhost.localdomain (Coremail) with SMTP id AQAAf8BxlsUaGYZmgJI6AA--.59898S3; Thu, 04 Jul 2024 11:38:03 +0800 (CST) From: Bibo Mao To: Paolo Bonzini , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Song Gao Cc: qemu-devel@nongnu.org Subject: [PATCH v2 1/4] hw/intc/loongson_ipi_common: Add loongson ipi common class Date: Thu, 4 Jul 2024 11:37:59 +0800 Message-Id: <20240704033802.3838618-2-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20240704033802.3838618-1-maobibo@loongson.cn> References: <20240704033802.3838618-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: AQAAf8BxlsUaGYZmgJI6AA--.59898S3 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1720064391381100003 Content-Type: text/plain; charset="utf-8" Loongson ipi common class and instance is created here, it comes from file loongson_ipi mostly. For the new added loongson ipi common class, there is four interfaces defined here: 1. Interfaces pre_save/post_load are used for future kvm child class 2. Interface get_iocsr_as can be used for different architectures, now MIPS 3A4000 and LoongArch 3A5000 machine use this ip, can inherit this common class. 3. Interace cpu_by_arch_id is added, by default generic function cpu_by_arch_id() is used to search vcpu from physical cpuid, it is generic searching method. Different machine may define other search methods such binary searching method. Signed-off-by: Bibo Mao --- hw/intc/loongson_ipi_common.c | 394 ++++++++++++++++++++++++++ include/hw/intc/loongson_ipi_common.h | 77 +++++ 2 files changed, 471 insertions(+) create mode 100644 hw/intc/loongson_ipi_common.c create mode 100644 include/hw/intc/loongson_ipi_common.h diff --git a/hw/intc/loongson_ipi_common.c b/hw/intc/loongson_ipi_common.c new file mode 100644 index 0000000000..3b8b077871 --- /dev/null +++ b/hw/intc/loongson_ipi_common.c @@ -0,0 +1,394 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Loongson ipi interrupt support + * + * Copyright (C) 2021 Loongson Technology Corporation Limited + */ + +#include "qemu/osdep.h" +#include "hw/boards.h" +#include "hw/sysbus.h" +#include "hw/intc/loongson_ipi_common.h" +#include "hw/irq.h" +#include "hw/qdev-properties.h" +#include "qapi/error.h" +#include "qemu/log.h" +#include "exec/address-spaces.h" +#include "exec/memory.h" +#include "migration/vmstate.h" +#include "trace.h" + +MemTxResult loongson_ipi_core_readl(void *opaque, hwaddr addr, + uint64_t *data, + unsigned size, MemTxAttrs attrs) +{ + IPICore *s =3D opaque; + uint64_t ret =3D 0; + int index =3D 0; + + addr &=3D 0xff; + switch (addr) { + case CORE_STATUS_OFF: + ret =3D s->status; + break; + case CORE_EN_OFF: + ret =3D s->en; + break; + case CORE_SET_OFF: + ret =3D 0; + break; + case CORE_CLEAR_OFF: + ret =3D 0; + break; + case CORE_BUF_20 ... CORE_BUF_38 + 4: + index =3D (addr - CORE_BUF_20) >> 2; + ret =3D s->buf[index]; + break; + default: + qemu_log_mask(LOG_UNIMP, "invalid read: %x", (uint32_t)addr); + break; + } + + trace_loongson_ipi_read(size, (uint64_t)addr, ret); + *data =3D ret; + return MEMTX_OK; +} + +static MemTxResult loongson_ipi_iocsr_readl(void *opaque, hwaddr addr, + uint64_t *data, + unsigned size, MemTxAttrs attr= s) +{ + LoongsonIPICommonState *ipi =3D opaque; + IPICore *s; + + if (attrs.requester_id >=3D ipi->num_cpu) { + return MEMTX_DECODE_ERROR; + } + + s =3D &ipi->cpu[attrs.requester_id]; + return loongson_ipi_core_readl(s, addr, data, size, attrs); +} + +static MemTxResult send_ipi_data(LoongsonIPICommonState *ipi, CPUState *cp= u, + uint64_t val, + hwaddr addr, MemTxAttrs attrs) +{ + int i, mask =3D 0, data =3D 0; + AddressSpace *iocsr_as; + LoongsonIPICommonClass *licc =3D LOONGSON_IPI_COMMON_GET_CLASS(ipi); + + iocsr_as =3D NULL; + if (licc->get_iocsr_as) { + iocsr_as =3D licc->get_iocsr_as(cpu); + } + + if (!iocsr_as) { + return MEMTX_DECODE_ERROR; + } + + /* + * bit 27-30 is mask for byte writing, + * if the mask is 0, we need not to do anything. + */ + if ((val >> 27) & 0xf) { + data =3D address_space_ldl_le(iocsr_as, addr, attrs, NULL); + for (i =3D 0; i < 4; i++) { + /* get mask for byte writing */ + if (val & (0x1 << (27 + i))) { + mask |=3D 0xff << (i * 8); + } + } + } + + data &=3D mask; + data |=3D (val >> 32) & ~mask; + address_space_stl_le(iocsr_as, addr, data, attrs, NULL); + + return MEMTX_OK; +} + +static CPUState *get_cpu_by_arch_id(LoongsonIPICommonState *ipi, uint32_t = cpuid) +{ + LoongsonIPICommonClass *licc =3D LOONGSON_IPI_COMMON_GET_CLASS(ipi); + + if (licc->cpu_by_arch_id) { + return licc->cpu_by_arch_id(cpuid); + } + + return cpu_by_arch_id(cpuid); +} + +static MemTxResult mail_send(LoongsonIPICommonState *ipi, uint64_t val, + MemTxAttrs attrs) +{ + uint32_t cpuid; + hwaddr addr; + CPUState *cs; + + cpuid =3D extract32(val, 16, 10); + cs =3D get_cpu_by_arch_id(ipi, cpuid); + if (cs =3D=3D NULL) { + return MEMTX_DECODE_ERROR; + } + + /* override requester_id */ + addr =3D SMP_IPI_MAILBOX + CORE_BUF_20 + (val & 0x1c); + attrs.requester_id =3D cs->cpu_index; + return send_ipi_data(ipi, cs, val, addr, attrs); +} + +static MemTxResult any_send(LoongsonIPICommonState *ipi, uint64_t val, + MemTxAttrs attrs) +{ + uint32_t cpuid; + hwaddr addr; + CPUState *cs; + + cpuid =3D extract32(val, 16, 10); + cs =3D get_cpu_by_arch_id(ipi, cpuid); + if (cs =3D=3D NULL) { + return MEMTX_DECODE_ERROR; + } + + /* override requester_id */ + addr =3D val & 0xffff; + attrs.requester_id =3D cs->cpu_index; + return send_ipi_data(ipi, cs, val, addr, attrs); +} + +MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr, + uint64_t val, unsigned size, + MemTxAttrs attrs) +{ + IPICore *s =3D opaque; + LoongsonIPICommonState *ipi =3D s->ipi; + int index =3D 0; + uint32_t cpuid; + uint8_t vector; + CPUState *cs; + + addr &=3D 0xff; + trace_loongson_ipi_write(size, (uint64_t)addr, val); + switch (addr) { + case CORE_STATUS_OFF: + qemu_log_mask(LOG_GUEST_ERROR, "can not be written"); + break; + case CORE_EN_OFF: + s->en =3D val; + break; + case CORE_SET_OFF: + s->status |=3D val; + if (s->status !=3D 0 && (s->status & s->en) !=3D 0) { + qemu_irq_raise(s->irq); + } + break; + case CORE_CLEAR_OFF: + s->status &=3D ~val; + if (s->status =3D=3D 0 && s->en !=3D 0) { + qemu_irq_lower(s->irq); + } + break; + case CORE_BUF_20 ... CORE_BUF_38 + 4: + index =3D (addr - CORE_BUF_20) >> 2; + s->buf[index] =3D val; + break; + case IOCSR_IPI_SEND: + cpuid =3D extract32(val, 16, 10); + /* IPI status vector */ + vector =3D extract8(val, 0, 5); + cs =3D get_cpu_by_arch_id(ipi, cpuid); + if (cs =3D=3D NULL || cs->cpu_index >=3D ipi->num_cpu) { + return MEMTX_DECODE_ERROR; + } + loongson_ipi_core_writel(&ipi->cpu[cs->cpu_index], CORE_SET_OFF, + BIT(vector), 4, attrs); + break; + default: + qemu_log_mask(LOG_UNIMP, "invalid write: %x", (uint32_t)addr); + break; + } + + return MEMTX_OK; +} + +static MemTxResult loongson_ipi_iocsr_writel(void *opaque, hwaddr addr, + uint64_t val, unsigned size, + MemTxAttrs attrs) +{ + LoongsonIPICommonState *ipi =3D opaque; + IPICore *s; + + if (attrs.requester_id >=3D ipi->num_cpu) { + return MEMTX_DECODE_ERROR; + } + + s =3D &ipi->cpu[attrs.requester_id]; + return loongson_ipi_core_writel(s, addr, val, size, attrs); +} + +static const MemoryRegionOps loongson_ipi_iocsr_ops =3D { + .read_with_attrs =3D loongson_ipi_iocsr_readl, + .write_with_attrs =3D loongson_ipi_iocsr_writel, + .impl.min_access_size =3D 4, + .impl.max_access_size =3D 4, + .valid.min_access_size =3D 4, + .valid.max_access_size =3D 8, + .endianness =3D DEVICE_LITTLE_ENDIAN, +}; + +/* mail send and any send only support writeq */ +static MemTxResult loongson_ipi_writeq(void *opaque, hwaddr addr, uint64_t= val, + unsigned size, MemTxAttrs attrs) +{ + MemTxResult ret =3D MEMTX_OK; + LoongsonIPICommonState *ipi =3D opaque; + + addr &=3D 0xfff; + switch (addr) { + case MAIL_SEND_OFFSET: + ret =3D mail_send(ipi, val, attrs); + break; + case ANY_SEND_OFFSET: + ret =3D any_send(ipi, val, attrs); + break; + default: + break; + } + + return ret; +} + +static const MemoryRegionOps loongson_ipi64_ops =3D { + .write_with_attrs =3D loongson_ipi_writeq, + .impl.min_access_size =3D 8, + .impl.max_access_size =3D 8, + .valid.min_access_size =3D 8, + .valid.max_access_size =3D 8, + .endianness =3D DEVICE_LITTLE_ENDIAN, +}; + +static void loongson_ipi_common_realize(DeviceState *dev, Error **errp) +{ + LoongsonIPICommonState *s =3D LOONGSON_IPI_COMMON(dev); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); + int i; + + if (s->num_cpu =3D=3D 0) { + error_setg(errp, "num-cpu must be at least 1"); + return; + } + + memory_region_init_io(&s->ipi_iocsr_mem, OBJECT(dev), + &loongson_ipi_iocsr_ops, + s, "loongson_ipi_iocsr", 0x48); + + /* loongson_ipi_iocsr performs re-entrant IO through ipi_send */ + s->ipi_iocsr_mem.disable_reentrancy_guard =3D true; + + sysbus_init_mmio(sbd, &s->ipi_iocsr_mem); + + memory_region_init_io(&s->ipi64_iocsr_mem, OBJECT(dev), + &loongson_ipi64_ops, + s, "loongson_ipi64_iocsr", 0x118); + sysbus_init_mmio(sbd, &s->ipi64_iocsr_mem); + + s->cpu =3D g_new0(IPICore, s->num_cpu); + if (s->cpu =3D=3D NULL) { + error_setg(errp, "Memory allocation for IPICore faile"); + return; + } + + for (i =3D 0; i < s->num_cpu; i++) { + s->cpu[i].ipi =3D s; + qdev_init_gpio_out(dev, &s->cpu[i].irq, 1); + } +} + +static int loongson_ipi_pre_save(void *opaque) +{ + LoongsonIPICommonState *s =3D (LoongsonIPICommonState *)opaque; + LoongsonIPICommonClass *c =3D LOONGSON_IPI_COMMON_GET_CLASS(s); + + if (c->pre_save) { + c->pre_save(s); + } + + return 0; +} + +static int loongson_ipi_post_load(void *opaque, int version_id) +{ + LoongsonIPICommonState *s =3D (LoongsonIPICommonState *)opaque; + LoongsonIPICommonClass *c =3D LOONGSON_IPI_COMMON_GET_CLASS(s); + + if (c->post_load) { + c->post_load(s); + } + return 0; +} + +static const VMStateDescription vmstate_ipi_core =3D { + .name =3D "ipi-single", + .version_id =3D 2, + .minimum_version_id =3D 2, + .fields =3D (const VMStateField[]) { + VMSTATE_UINT32(status, IPICore), + VMSTATE_UINT32(en, IPICore), + VMSTATE_UINT32(set, IPICore), + VMSTATE_UINT32(clear, IPICore), + VMSTATE_UINT32_ARRAY(buf, IPICore, IPI_MBX_NUM * 2), + VMSTATE_END_OF_LIST() + } +}; + +static const VMStateDescription vmstate_loongson_ipi =3D { + /* Fixed name to keep compatible */ + .name =3D "loongson_ipi", + .pre_save =3D loongson_ipi_pre_save, + .post_load =3D loongson_ipi_post_load, + .version_id =3D 2, + .minimum_version_id =3D 2, + .fields =3D (const VMStateField[]) { + VMSTATE_STRUCT_VARRAY_POINTER_UINT32(cpu, LoongsonIPICommonState, + num_cpu, vmstate_ipi_core, IPICore), + VMSTATE_END_OF_LIST() + } +}; + +static Property ipi_properties[] =3D { + DEFINE_PROP_UINT32("num-cpu", LoongsonIPICommonState, num_cpu, 1), + DEFINE_PROP_END_OF_LIST(), +}; + +static void loongson_ipi_common_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->realize =3D loongson_ipi_common_realize; + device_class_set_props(dc, ipi_properties); + dc->vmsd =3D &vmstate_loongson_ipi; +} + +static void loongson_ipi_common_finalize(Object *obj) +{ + LoongsonIPICommonState *s =3D LOONGSON_IPI_COMMON(obj); + + g_free(s->cpu); +} + +static const TypeInfo loongson_ipi_common_info =3D { + .name =3D TYPE_LOONGSON_IPI_COMMON, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(LoongsonIPICommonState), + .class_size =3D sizeof(LoongsonIPICommonClass), + .class_init =3D loongson_ipi_common_class_init, + .instance_finalize =3D loongson_ipi_common_finalize, + .abstract =3D true, +}; + +static void loongson_ipi_common_register_types(void) +{ + type_register_static(&loongson_ipi_common_info); +} + +type_init(loongson_ipi_common_register_types) diff --git a/include/hw/intc/loongson_ipi_common.h b/include/hw/intc/loongs= on_ipi_common.h new file mode 100644 index 0000000000..4b75c4572a --- /dev/null +++ b/include/hw/intc/loongson_ipi_common.h @@ -0,0 +1,77 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Loongson ipi interrupt header files + * + * Copyright (C) 2021 Loongson Technology Corporation Limited + */ + +#ifndef HW_LOONGSON_IPI_COMMON_H +#define HW_LOONGSON_IPI_COMMON_H + +#include "hw/sysbus.h" +#include "hw/core/cpu.h" +#include "qom/object.h" + +/* Mainy used by iocsr read and write */ +#define SMP_IPI_MAILBOX 0x1000ULL +#define CORE_STATUS_OFF 0x0 +#define CORE_EN_OFF 0x4 +#define CORE_SET_OFF 0x8 +#define CORE_CLEAR_OFF 0xc +#define CORE_BUF_20 0x20 +#define CORE_BUF_28 0x28 +#define CORE_BUF_30 0x30 +#define CORE_BUF_38 0x38 +#define IOCSR_IPI_SEND 0x40 +#define IOCSR_MAIL_SEND 0x48 +#define IOCSR_ANY_SEND 0x158 + +#define MAIL_SEND_ADDR (SMP_IPI_MAILBOX + IOCSR_MAIL_SEND) +#define MAIL_SEND_OFFSET 0 +#define ANY_SEND_OFFSET (IOCSR_ANY_SEND - IOCSR_MAIL_SEND) + +#define IPI_MBX_NUM 4 + +#define TYPE_LOONGSON_IPI_COMMON "loongson_ipi_common" +typedef struct LoongsonIPICommonClass LoongsonIPICommonClass; +typedef struct LoongsonIPICommonState LoongsonIPICommonState; +DECLARE_OBJ_CHECKERS(LoongsonIPICommonState, LoongsonIPICommonClass, + LOONGSON_IPI_COMMON, TYPE_LOONGSON_IPI_COMMON) + +typedef struct IPICore { + LoongsonIPICommonState *ipi; + uint32_t status; + uint32_t en; + uint32_t set; + uint32_t clear; + /* 64bit buf divide into 2 32bit buf */ + uint32_t buf[IPI_MBX_NUM * 2]; + qemu_irq irq; +} IPICore; + +struct LoongsonIPICommonState { + SysBusDevice parent_obj; + MemoryRegion ipi_iocsr_mem; + MemoryRegion ipi64_iocsr_mem; + uint32_t num_cpu; + IPICore *cpu; +}; + +struct LoongsonIPICommonClass { + /*< private >*/ + SysBusDeviceClass parent_class; + /*< public >*/ + + void (*pre_save)(LoongsonIPICommonState *s); + void (*post_load)(LoongsonIPICommonState *s); + AddressSpace *(*get_iocsr_as)(CPUState *cpu); + CPUState *(*cpu_by_arch_id)(int64_t id); +}; + +MemTxResult loongson_ipi_core_readl(void *opaque, hwaddr addr, + uint64_t *data, + unsigned size, MemTxAttrs attrs); +MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr, + uint64_t val, unsigned size, + MemTxAttrs attrs); +#endif --=20 2.39.3 From nobody Sun Nov 24 20:41:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1720064357452423.53743180800586; Wed, 3 Jul 2024 20:39:17 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sPDIZ-0007tM-1p; Wed, 03 Jul 2024 23:38:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sPDIW-0007qj-9B for qemu-devel@nongnu.org; Wed, 03 Jul 2024 23:38:16 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sPDIS-0003AH-P7 for qemu-devel@nongnu.org; Wed, 03 Jul 2024 23:38:16 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8AxG_AbGYZmDs0AAA--.2457S3; Thu, 04 Jul 2024 11:38:03 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by localhost.localdomain (Coremail) with SMTP id AQAAf8BxlsUaGYZmgJI6AA--.59898S4; Thu, 04 Jul 2024 11:38:03 +0800 (CST) From: Bibo Mao To: Paolo Bonzini , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Song Gao Cc: qemu-devel@nongnu.org Subject: [PATCH v2 2/4] hw/intc/loongarch_ipi: Add loongarch ipi support Date: Thu, 4 Jul 2024 11:38:00 +0800 Message-Id: <20240704033802.3838618-3-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20240704033802.3838618-1-maobibo@loongson.cn> References: <20240704033802.3838618-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: AQAAf8BxlsUaGYZmgJI6AA--.59898S4 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1720064359099100003 Content-Type: text/plain; charset="utf-8" Loongarch ipi is added herei, it inherits from class TYPE_LOONGSON_IPI_COMMON, and two interfaces get_iocsr_as() and cpu_by_arch_id() are added for Loongarch 3A5000 machine. It can be used when ipi is emulated in userspace with kvm mode. Signed-off-by: Bibo Mao --- hw/intc/loongarch_ipi.c | 80 +++++++++++++++++++++++++++++++++ include/hw/intc/loongarch_ipi.h | 33 ++++++++++++++ 2 files changed, 113 insertions(+) create mode 100644 hw/intc/loongarch_ipi.c create mode 100644 include/hw/intc/loongarch_ipi.h diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c new file mode 100644 index 0000000000..91689c35c0 --- /dev/null +++ b/hw/intc/loongarch_ipi.c @@ -0,0 +1,80 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Loongarch ipi interrupt support + * + * Copyright (C) 2024 Loongson Technology Corporation Limited + */ + +#include "qemu/osdep.h" +#include "hw/boards.h" +#include "hw/sysbus.h" +#include "hw/intc/loongarch_ipi.h" +#include "hw/irq.h" +#include "hw/qdev-properties.h" +#include "qapi/error.h" +#include "qemu/log.h" +#include "exec/address-spaces.h" +#include "migration/vmstate.h" +#include "target/loongarch/cpu.h" +#include "trace.h" + +static AddressSpace *get_iocsr_as(CPUState *cpu) +{ + return LOONGARCH_CPU(cpu)->env.address_space_iocsr; +} + +static int archid_cmp(const void *a, const void *b) +{ + CPUArchId *archid_a =3D (CPUArchId *)a; + CPUArchId *archid_b =3D (CPUArchId *)b; + + return archid_a->arch_id - archid_b->arch_id; +} + +static CPUArchId *find_cpu_by_archid(MachineState *ms, uint32_t id) +{ + CPUArchId apic_id, *found_cpu; + + apic_id.arch_id =3D id; + found_cpu =3D bsearch(&apic_id, ms->possible_cpus->cpus, + ms->possible_cpus->len, sizeof(*ms->possible_cpus->cpus), + archid_cmp); + + return found_cpu; +} + +static CPUState *get_cpu_by_archid(int64_t arch_id) +{ + MachineState *machine =3D MACHINE(qdev_get_machine()); + CPUArchId *archid; + + archid =3D find_cpu_by_archid(machine, arch_id); + if (archid) { + return CPU(archid->cpu); + } + + return NULL; +} + +static void loongarch_ipi_class_init(ObjectClass *klass, void *data) +{ + LoongsonIPICommonClass *licc =3D LOONGSON_IPI_COMMON_CLASS(klass); + + licc->get_iocsr_as =3D get_iocsr_as; + licc->cpu_by_arch_id =3D get_cpu_by_archid; +} + +static const TypeInfo loongarch_ipi_info =3D { + .name =3D TYPE_LOONGARCH_IPI, + .parent =3D TYPE_LOONGSON_IPI_COMMON, + .instance_size =3D sizeof(LoongarchIPIState), + .class_size =3D sizeof(LoongarchIPIClass), + .class_init =3D loongarch_ipi_class_init, +}; + +static void loongarch_ipi_register_types(void) +{ + type_register_static(&loongarch_ipi_info); +} + +type_init(loongarch_ipi_register_types) diff --git a/include/hw/intc/loongarch_ipi.h b/include/hw/intc/loongarch_ip= i.h new file mode 100644 index 0000000000..451bbcff5c --- /dev/null +++ b/include/hw/intc/loongarch_ipi.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Loongarch ipi interrupt header files + * + * Copyright (C) 2024 Loongson Technology Corporation Limited + */ + +#ifndef HW_LOONGARCH_IPI_H +#define HW_LOONGARCH_IPI_H + +#include "qom/object.h" +#include "hw/intc/loongson_ipi_common.h" +#include "hw/sysbus.h" + +#define TYPE_LOONGARCH_IPI "loongarch_ipi" +typedef struct LoongarchIPIClass LoongarchIPIClass; +typedef struct LoongarchIPIState LoongarchIPIState; +DECLARE_OBJ_CHECKERS(LoongarchIPIState, LoongarchIPIClass, + LOONGARCH_IPI, TYPE_LOONGARCH_IPI) + +struct LoongarchIPIState { + LoongsonIPICommonState parent_obj; +}; + +struct LoongarchIPIClass { + /*< private >*/ + LoongsonIPICommonClass parent_class; + /*< public >*/ + + DeviceRealize parent_realize; +}; + +#endif --=20 2.39.3 From nobody Sun Nov 24 20:41:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1720064391557124.07839513958208; Wed, 3 Jul 2024 20:39:51 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sPDJE-0008PC-WE; Wed, 03 Jul 2024 23:39:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sPDJ7-0008Le-BV for qemu-devel@nongnu.org; Wed, 03 Jul 2024 23:38:53 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sPDJ4-0005Dn-Ex for qemu-devel@nongnu.org; Wed, 03 Jul 2024 23:38:52 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8AxH_FHGYZmIs0AAA--.2801S3; Thu, 04 Jul 2024 11:38:47 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by localhost.localdomain (Coremail) with SMTP id AQAAf8BxlsUaGYZmgJI6AA--.59898S5; Thu, 04 Jul 2024 11:38:03 +0800 (CST) From: Bibo Mao To: Paolo Bonzini , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Song Gao Cc: qemu-devel@nongnu.org Subject: [PATCH v2 3/4] hw/loongarch/virt: Replace loongson ipi with loongarch ipi Date: Thu, 4 Jul 2024 11:38:01 +0800 Message-Id: <20240704033802.3838618-4-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20240704033802.3838618-1-maobibo@loongson.cn> References: <20240704033802.3838618-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: AQAAf8BxlsUaGYZmgJI6AA--.59898S5 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1720064393207100011 Content-Type: text/plain; charset="utf-8" Loongarch ipi inherits from class LoongsonIPICommonClass, and it only contains Loongarch 3A5000 virt machine specific interfaces, rather than mix different machine implementations together. Signed-off-by: Bibo Mao --- hw/intc/Kconfig | 3 +++ hw/intc/meson.build | 1 + hw/loongarch/Kconfig | 2 +- hw/loongarch/virt.c | 4 ++-- include/hw/loongarch/virt.h | 1 - 5 files changed, 7 insertions(+), 4 deletions(-) diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig index 58b6d3a710..870f537236 100644 --- a/hw/intc/Kconfig +++ b/hw/intc/Kconfig @@ -90,6 +90,9 @@ config M68K_IRQC config LOONGSON_IPI bool =20 +config LOONGARCH_IPI + bool + config LOONGARCH_PCH_PIC bool select UNIMP diff --git a/hw/intc/meson.build b/hw/intc/meson.build index afd1aa51ee..b7fce2f375 100644 --- a/hw/intc/meson.build +++ b/hw/intc/meson.build @@ -70,6 +70,7 @@ specific_ss.add(when: ['CONFIG_KVM', 'CONFIG_XIVE'], if_true: files('spapr_xive_kvm.c')) specific_ss.add(when: 'CONFIG_M68K_IRQC', if_true: files('m68k_irqc.c')) specific_ss.add(when: 'CONFIG_LOONGSON_IPI', if_true: files('loongson_ipi.= c')) +specific_ss.add(when: 'CONFIG_LOONGARCH_IPI', if_true: files('loongarch_ip= i.c', 'loongson_ipi_common.c')) specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_PIC', if_true: files('loongarc= h_pch_pic.c')) specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_MSI', if_true: files('loongarc= h_pch_msi.c')) specific_ss.add(when: 'CONFIG_LOONGARCH_EXTIOI', if_true: files('loongarch= _extioi.c')) diff --git a/hw/loongarch/Kconfig b/hw/loongarch/Kconfig index 90a0dba9d5..830cfef72d 100644 --- a/hw/loongarch/Kconfig +++ b/hw/loongarch/Kconfig @@ -11,7 +11,7 @@ config LOONGARCH_VIRT select SERIAL select VIRTIO_PCI select PLATFORM_BUS - select LOONGSON_IPI + select LOONGARCH_IPI select LOONGARCH_PCH_PIC select LOONGARCH_PCH_MSI select LOONGARCH_EXTIOI diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c index 8be2d2ff6a..6bef2f1165 100644 --- a/hw/loongarch/virt.c +++ b/hw/loongarch/virt.c @@ -23,7 +23,7 @@ #include "net/net.h" #include "hw/loader.h" #include "elf.h" -#include "hw/intc/loongson_ipi.h" +#include "hw/intc/loongarch_ipi.h" #include "hw/intc/loongarch_extioi.h" #include "hw/intc/loongarch_pch_pic.h" #include "hw/intc/loongarch_pch_msi.h" @@ -788,7 +788,7 @@ static void virt_irq_init(LoongArchVirtMachineState *lv= ms) */ =20 /* Create IPI device */ - ipi =3D qdev_new(TYPE_LOONGSON_IPI); + ipi =3D qdev_new(TYPE_LOONGARCH_IPI); qdev_prop_set_uint32(ipi, "num-cpu", ms->smp.cpus); sysbus_realize_and_unref(SYS_BUS_DEVICE(ipi), &error_fatal); =20 diff --git a/include/hw/loongarch/virt.h b/include/hw/loongarch/virt.h index 8fdfacf268..91216418c8 100644 --- a/include/hw/loongarch/virt.h +++ b/include/hw/loongarch/virt.h @@ -11,7 +11,6 @@ #include "target/loongarch/cpu.h" #include "hw/boards.h" #include "qemu/queue.h" -#include "hw/intc/loongson_ipi.h" #include "hw/block/flash.h" #include "hw/loongarch/boot.h" =20 --=20 2.39.3 From nobody Sun Nov 24 20:41:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1720064375585599.1044929819935; Wed, 3 Jul 2024 20:39:35 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sPDIb-0007uE-Hq; Wed, 03 Jul 2024 23:38:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sPDIW-0007qw-OU for qemu-devel@nongnu.org; Wed, 03 Jul 2024 23:38:17 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sPDIS-0003AG-PB for qemu-devel@nongnu.org; Wed, 03 Jul 2024 23:38:16 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8BxnuscGYZmFs0AAA--.2377S3; Thu, 04 Jul 2024 11:38:04 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by localhost.localdomain (Coremail) with SMTP id AQAAf8BxlsUaGYZmgJI6AA--.59898S6; Thu, 04 Jul 2024 11:38:03 +0800 (CST) From: Bibo Mao To: Paolo Bonzini , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Song Gao Cc: qemu-devel@nongnu.org Subject: [PATCH v2 4/4] hw/intc/loongson_ipi: reconstruct driver inherit from common class Date: Thu, 4 Jul 2024 11:38:02 +0800 Message-Id: <20240704033802.3838618-5-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20240704033802.3838618-1-maobibo@loongson.cn> References: <20240704033802.3838618-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: AQAAf8BxlsUaGYZmgJI6AA--.59898S6 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1720064377173100003 Content-Type: text/plain; charset="utf-8" Like loongarch ipi, reconstruct this driver by inheriting class LoongsonIPICommonClass. Add extra function loongson_ipi_realize() to implement mmio memory region. Signed-off-by: Bibo Mao --- hw/intc/loongson_ipi.c | 330 +++------------------------------ hw/intc/meson.build | 2 +- include/hw/intc/loongson_ipi.h | 54 ++---- 3 files changed, 41 insertions(+), 345 deletions(-) diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c index e6a7142480..42c3cff9ac 100644 --- a/hw/intc/loongson_ipi.c +++ b/hw/intc/loongson_ipi.c @@ -15,213 +15,16 @@ #include "qemu/log.h" #include "exec/address-spaces.h" #include "migration/vmstate.h" -#ifdef TARGET_LOONGARCH64 -#include "target/loongarch/cpu.h" -#endif -#ifdef TARGET_MIPS #include "target/mips/cpu.h" -#endif #include "trace.h" =20 -static MemTxResult loongson_ipi_core_readl(void *opaque, hwaddr addr, - uint64_t *data, - unsigned size, MemTxAttrs attrs) +static AddressSpace *get_iocsr_as(CPUState *cpu) { - IPICore *s =3D opaque; - uint64_t ret =3D 0; - int index =3D 0; - - addr &=3D 0xff; - switch (addr) { - case CORE_STATUS_OFF: - ret =3D s->status; - break; - case CORE_EN_OFF: - ret =3D s->en; - break; - case CORE_SET_OFF: - ret =3D 0; - break; - case CORE_CLEAR_OFF: - ret =3D 0; - break; - case CORE_BUF_20 ... CORE_BUF_38 + 4: - index =3D (addr - CORE_BUF_20) >> 2; - ret =3D s->buf[index]; - break; - default: - qemu_log_mask(LOG_UNIMP, "invalid read: %x", (uint32_t)addr); - break; - } - - trace_loongson_ipi_read(size, (uint64_t)addr, ret); - *data =3D ret; - return MEMTX_OK; -} - -static MemTxResult loongson_ipi_iocsr_readl(void *opaque, hwaddr addr, - uint64_t *data, - unsigned size, MemTxAttrs attr= s) -{ - LoongsonIPI *ipi =3D opaque; - IPICore *s; - - if (attrs.requester_id >=3D ipi->num_cpu) { - return MEMTX_DECODE_ERROR; - } - - s =3D &ipi->cpu[attrs.requester_id]; - return loongson_ipi_core_readl(s, addr, data, size, attrs); -} - -static AddressSpace *get_cpu_iocsr_as(CPUState *cpu) -{ -#ifdef TARGET_LOONGARCH64 - return LOONGARCH_CPU(cpu)->env.address_space_iocsr; -#endif -#ifdef TARGET_MIPS if (ase_lcsr_available(&MIPS_CPU(cpu)->env)) { return &MIPS_CPU(cpu)->env.iocsr.as; } -#endif - return NULL; -} - -static MemTxResult send_ipi_data(CPUState *cpu, uint64_t val, hwaddr addr, - MemTxAttrs attrs) -{ - int i, mask =3D 0, data =3D 0; - AddressSpace *iocsr_as =3D get_cpu_iocsr_as(cpu); - - if (!iocsr_as) { - return MEMTX_DECODE_ERROR; - } - - /* - * bit 27-30 is mask for byte writing, - * if the mask is 0, we need not to do anything. - */ - if ((val >> 27) & 0xf) { - data =3D address_space_ldl(iocsr_as, addr, attrs, NULL); - for (i =3D 0; i < 4; i++) { - /* get mask for byte writing */ - if (val & (0x1 << (27 + i))) { - mask |=3D 0xff << (i * 8); - } - } - } - - data &=3D mask; - data |=3D (val >> 32) & ~mask; - address_space_stl(iocsr_as, addr, data, attrs, NULL); - - return MEMTX_OK; -} - -static MemTxResult mail_send(uint64_t val, MemTxAttrs attrs) -{ - uint32_t cpuid; - hwaddr addr; - CPUState *cs; - - cpuid =3D extract32(val, 16, 10); - cs =3D cpu_by_arch_id(cpuid); - if (cs =3D=3D NULL) { - return MEMTX_DECODE_ERROR; - } - - /* override requester_id */ - addr =3D SMP_IPI_MAILBOX + CORE_BUF_20 + (val & 0x1c); - attrs.requester_id =3D cs->cpu_index; - return send_ipi_data(cs, val, addr, attrs); -} - -static MemTxResult any_send(uint64_t val, MemTxAttrs attrs) -{ - uint32_t cpuid; - hwaddr addr; - CPUState *cs; - - cpuid =3D extract32(val, 16, 10); - cs =3D cpu_by_arch_id(cpuid); - if (cs =3D=3D NULL) { - return MEMTX_DECODE_ERROR; - } - - /* override requester_id */ - addr =3D val & 0xffff; - attrs.requester_id =3D cs->cpu_index; - return send_ipi_data(cs, val, addr, attrs); -} - -static MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr, - uint64_t val, unsigned size, - MemTxAttrs attrs) -{ - IPICore *s =3D opaque; - LoongsonIPI *ipi =3D s->ipi; - int index =3D 0; - uint32_t cpuid; - uint8_t vector; - CPUState *cs; - - addr &=3D 0xff; - trace_loongson_ipi_write(size, (uint64_t)addr, val); - switch (addr) { - case CORE_STATUS_OFF: - qemu_log_mask(LOG_GUEST_ERROR, "can not be written"); - break; - case CORE_EN_OFF: - s->en =3D val; - break; - case CORE_SET_OFF: - s->status |=3D val; - if (s->status !=3D 0 && (s->status & s->en) !=3D 0) { - qemu_irq_raise(s->irq); - } - break; - case CORE_CLEAR_OFF: - s->status &=3D ~val; - if (s->status =3D=3D 0 && s->en !=3D 0) { - qemu_irq_lower(s->irq); - } - break; - case CORE_BUF_20 ... CORE_BUF_38 + 4: - index =3D (addr - CORE_BUF_20) >> 2; - s->buf[index] =3D val; - break; - case IOCSR_IPI_SEND: - cpuid =3D extract32(val, 16, 10); - /* IPI status vector */ - vector =3D extract8(val, 0, 5); - cs =3D cpu_by_arch_id(cpuid); - if (cs =3D=3D NULL || cs->cpu_index >=3D ipi->num_cpu) { - return MEMTX_DECODE_ERROR; - } - loongson_ipi_core_writel(&ipi->cpu[cs->cpu_index], CORE_SET_OFF, - BIT(vector), 4, attrs); - break; - default: - qemu_log_mask(LOG_UNIMP, "invalid write: %x", (uint32_t)addr); - break; - } =20 - return MEMTX_OK; -} - -static MemTxResult loongson_ipi_iocsr_writel(void *opaque, hwaddr addr, - uint64_t val, unsigned size, - MemTxAttrs attrs) -{ - LoongsonIPI *ipi =3D opaque; - IPICore *s; - - if (attrs.requester_id >=3D ipi->num_cpu) { - return MEMTX_DECODE_ERROR; - } - - s =3D &ipi->cpu[attrs.requester_id]; - return loongson_ipi_core_writel(s, addr, val, size, attrs); + return NULL; } =20 static const MemoryRegionOps loongson_ipi_core_ops =3D { @@ -234,139 +37,54 @@ static const MemoryRegionOps loongson_ipi_core_ops = =3D { .endianness =3D DEVICE_LITTLE_ENDIAN, }; =20 -static const MemoryRegionOps loongson_ipi_iocsr_ops =3D { - .read_with_attrs =3D loongson_ipi_iocsr_readl, - .write_with_attrs =3D loongson_ipi_iocsr_writel, - .impl.min_access_size =3D 4, - .impl.max_access_size =3D 4, - .valid.min_access_size =3D 4, - .valid.max_access_size =3D 8, - .endianness =3D DEVICE_LITTLE_ENDIAN, -}; - -/* mail send and any send only support writeq */ -static MemTxResult loongson_ipi_writeq(void *opaque, hwaddr addr, uint64_t= val, - unsigned size, MemTxAttrs attrs) -{ - MemTxResult ret =3D MEMTX_OK; - - addr &=3D 0xfff; - switch (addr) { - case MAIL_SEND_OFFSET: - ret =3D mail_send(val, attrs); - break; - case ANY_SEND_OFFSET: - ret =3D any_send(val, attrs); - break; - default: - break; - } - - return ret; -} - -static const MemoryRegionOps loongson_ipi64_ops =3D { - .write_with_attrs =3D loongson_ipi_writeq, - .impl.min_access_size =3D 8, - .impl.max_access_size =3D 8, - .valid.min_access_size =3D 8, - .valid.max_access_size =3D 8, - .endianness =3D DEVICE_LITTLE_ENDIAN, -}; =20 static void loongson_ipi_realize(DeviceState *dev, Error **errp) { - LoongsonIPI *s =3D LOONGSON_IPI(dev); + LoongsonIPIState *s =3D LOONGSON_IPI(dev); + LoongsonIPIClass *lic =3D LOONGSON_IPI_GET_CLASS(s); SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); + Error *local_err =3D NULL; int i; =20 - if (s->num_cpu =3D=3D 0) { - error_setg(errp, "num-cpu must be at least 1"); - return; - } - - memory_region_init_io(&s->ipi_iocsr_mem, OBJECT(dev), - &loongson_ipi_iocsr_ops, - s, "loongson_ipi_iocsr", 0x48); - - /* loongson_ipi_iocsr performs re-entrant IO through ipi_send */ - s->ipi_iocsr_mem.disable_reentrancy_guard =3D true; - - sysbus_init_mmio(sbd, &s->ipi_iocsr_mem); - - memory_region_init_io(&s->ipi64_iocsr_mem, OBJECT(dev), - &loongson_ipi64_ops, - s, "loongson_ipi64_iocsr", 0x118); - sysbus_init_mmio(sbd, &s->ipi64_iocsr_mem); - - s->cpu =3D g_new0(IPICore, s->num_cpu); - if (s->cpu =3D=3D NULL) { - error_setg(errp, "Memory allocation for IPICore faile"); + lic->parent_realize(dev, &local_err); + if (local_err) { + error_propagate(errp, local_err); return; } =20 - for (i =3D 0; i < s->num_cpu; i++) { - s->cpu[i].ipi =3D s; - s->cpu[i].ipi_mmio_mem =3D g_new0(MemoryRegion, 1); + s->ipi_mmio_mem =3D g_new0(MemoryRegion, s->parent_obj.num_cpu); + for (i =3D 0; i < s->parent_obj.num_cpu; i++) { g_autofree char *name =3D g_strdup_printf("loongson_ipi_cpu%d_mmio= ", i); - memory_region_init_io(s->cpu[i].ipi_mmio_mem, OBJECT(dev), - &loongson_ipi_core_ops, &s->cpu[i], name, 0x= 48); - sysbus_init_mmio(sbd, s->cpu[i].ipi_mmio_mem); - - qdev_init_gpio_out(dev, &s->cpu[i].irq, 1); + memory_region_init_io(s->ipi_mmio_mem + i, OBJECT(dev), + &loongson_ipi_core_ops, &s->parent_obj.cpu[i= ], + name, 0x48); + sysbus_init_mmio(sbd, s->ipi_mmio_mem + i); } } =20 -static const VMStateDescription vmstate_ipi_core =3D { - .name =3D "ipi-single", - .version_id =3D 2, - .minimum_version_id =3D 2, - .fields =3D (const VMStateField[]) { - VMSTATE_UINT32(status, IPICore), - VMSTATE_UINT32(en, IPICore), - VMSTATE_UINT32(set, IPICore), - VMSTATE_UINT32(clear, IPICore), - VMSTATE_UINT32_ARRAY(buf, IPICore, IPI_MBX_NUM * 2), - VMSTATE_END_OF_LIST() - } -}; - -static const VMStateDescription vmstate_loongson_ipi =3D { - .name =3D TYPE_LOONGSON_IPI, - .version_id =3D 2, - .minimum_version_id =3D 2, - .fields =3D (const VMStateField[]) { - VMSTATE_STRUCT_VARRAY_POINTER_UINT32(cpu, LoongsonIPI, num_cpu, - vmstate_ipi_core, IPICore), - VMSTATE_END_OF_LIST() - } -}; - -static Property ipi_properties[] =3D { - DEFINE_PROP_UINT32("num-cpu", LoongsonIPI, num_cpu, 1), - DEFINE_PROP_END_OF_LIST(), -}; - static void loongson_ipi_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); + LoongsonIPICommonClass *licc =3D LOONGSON_IPI_COMMON_CLASS(klass); + LoongsonIPIClass *lic =3D LOONGSON_IPI_CLASS(klass); =20 - dc->realize =3D loongson_ipi_realize; - device_class_set_props(dc, ipi_properties); - dc->vmsd =3D &vmstate_loongson_ipi; + device_class_set_parent_realize(dc, loongson_ipi_realize, + &lic->parent_realize); + licc->get_iocsr_as =3D get_iocsr_as; } =20 static void loongson_ipi_finalize(Object *obj) { - LoongsonIPI *s =3D LOONGSON_IPI(obj); + LoongsonIPIState *s =3D LOONGSON_IPI(obj); =20 - g_free(s->cpu); + g_free(s->ipi_mmio_mem); } =20 static const TypeInfo loongson_ipi_info =3D { .name =3D TYPE_LOONGSON_IPI, - .parent =3D TYPE_SYS_BUS_DEVICE, - .instance_size =3D sizeof(LoongsonIPI), + .parent =3D TYPE_LOONGSON_IPI_COMMON, + .instance_size =3D sizeof(LoongsonIPIState), + .class_size =3D sizeof(LoongsonIPIClass), .class_init =3D loongson_ipi_class_init, .instance_finalize =3D loongson_ipi_finalize, }; diff --git a/hw/intc/meson.build b/hw/intc/meson.build index b7fce2f375..81b72d57bc 100644 --- a/hw/intc/meson.build +++ b/hw/intc/meson.build @@ -69,7 +69,7 @@ specific_ss.add(when: 'CONFIG_XIVE', if_true: files('xive= .c')) specific_ss.add(when: ['CONFIG_KVM', 'CONFIG_XIVE'], if_true: files('spapr_xive_kvm.c')) specific_ss.add(when: 'CONFIG_M68K_IRQC', if_true: files('m68k_irqc.c')) -specific_ss.add(when: 'CONFIG_LOONGSON_IPI', if_true: files('loongson_ipi.= c')) +specific_ss.add(when: 'CONFIG_LOONGSON_IPI', if_true: files('loongson_ipi.= c', 'loongson_ipi_common.c')) specific_ss.add(when: 'CONFIG_LOONGARCH_IPI', if_true: files('loongarch_ip= i.c', 'loongson_ipi_common.c')) specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_PIC', if_true: files('loongarc= h_pch_pic.c')) specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_MSI', if_true: files('loongarc= h_pch_msi.c')) diff --git a/include/hw/intc/loongson_ipi.h b/include/hw/intc/loongson_ipi.h index 3f795edbf3..acf2b9d9a6 100644 --- a/include/hw/intc/loongson_ipi.h +++ b/include/hw/intc/loongson_ipi.h @@ -8,49 +8,27 @@ #ifndef HW_LOONGSON_IPI_H #define HW_LOONGSON_IPI_H =20 +#include "qom/object.h" +#include "hw/intc/loongson_ipi_common.h" #include "hw/sysbus.h" =20 -/* Mainy used by iocsr read and write */ -#define SMP_IPI_MAILBOX 0x1000ULL -#define CORE_STATUS_OFF 0x0 -#define CORE_EN_OFF 0x4 -#define CORE_SET_OFF 0x8 -#define CORE_CLEAR_OFF 0xc -#define CORE_BUF_20 0x20 -#define CORE_BUF_28 0x28 -#define CORE_BUF_30 0x30 -#define CORE_BUF_38 0x38 -#define IOCSR_IPI_SEND 0x40 -#define IOCSR_MAIL_SEND 0x48 -#define IOCSR_ANY_SEND 0x158 +#define TYPE_LOONGSON_IPI "loongson_ipi" +typedef struct LoongsonIPIClass LoongsonIPIClass; +typedef struct LoongsonIPIState LoongsonIPIState; +DECLARE_OBJ_CHECKERS(LoongsonIPIState, LoongsonIPIClass, + LOONGSON_IPI, TYPE_LOONGSON_IPI) =20 -#define MAIL_SEND_ADDR (SMP_IPI_MAILBOX + IOCSR_MAIL_SEND) -#define MAIL_SEND_OFFSET 0 -#define ANY_SEND_OFFSET (IOCSR_ANY_SEND - IOCSR_MAIL_SEND) - -#define IPI_MBX_NUM 4 - -#define TYPE_LOONGSON_IPI "loongson_ipi" -OBJECT_DECLARE_SIMPLE_TYPE(LoongsonIPI, LOONGSON_IPI) - -typedef struct IPICore { - LoongsonIPI *ipi; +struct LoongsonIPIState { + LoongsonIPICommonState parent_obj; MemoryRegion *ipi_mmio_mem; - uint32_t status; - uint32_t en; - uint32_t set; - uint32_t clear; - /* 64bit buf divide into 2 32bit buf */ - uint32_t buf[IPI_MBX_NUM * 2]; - qemu_irq irq; -} IPICore; +}; + +struct LoongsonIPIClass { + /*< private >*/ + LoongsonIPICommonClass parent_class; + /*< public >*/ =20 -struct LoongsonIPI { - SysBusDevice parent_obj; - MemoryRegion ipi_iocsr_mem; - MemoryRegion ipi64_iocsr_mem; - uint32_t num_cpu; - IPICore *cpu; + DeviceRealize parent_realize; }; =20 #endif --=20 2.39.3