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Tsirkin" , Paolo Bonzini , Richard Henderson , Eric Blake , Markus Armbruster , Marcelo Tosatti , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Peter Maydell , Jonathan Cameron , Sia Jee Heng Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Zhenyu Wang , Dapeng Mi , Yongwei Ma , Zhao Liu Subject: [PATCH 8/8] qemu-options: Add the description of smp-cache object Date: Thu, 4 Jul 2024 11:16:03 +0800 Message-Id: <20240704031603.1744546-9-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240704031603.1744546-1-zhao1.liu@intel.com> References: <20240704031603.1744546-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.9; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1720062138634100005 Content-Type: text/plain; charset="utf-8" Signed-off-by: Zhao Liu --- Changes since RFC v2: * Rewrote the document of smp-cache object. Changes since RFC v1: * Use "*_cache=3Dtopo_level" as -smp example as the original "level" term for a cache has a totally different meaning. (Jonathan) --- qemu-options.hx | 58 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/qemu-options.hx b/qemu-options.hx index 8ca7f34ef0c8..4b84f4508a6e 100644 --- a/qemu-options.hx +++ b/qemu-options.hx @@ -159,6 +159,15 @@ SRST :: =20 -machine cxl-fmw.0.targets.0=3Dcxl.0,cxl-fmw.0.targets.1=3Dcxl= .1,cxl-fmw.0.size=3D128G,cxl-fmw.0.interleave-granularity=3D512 + + ``smp-cache=3D'id'`` + Allows to configure cache property (now only the cache topology le= vel). + + For example: + :: + + -object '{"qom-type":"smp-cache","id":"cache","caches":[{"name= ":"l1d","topo":"core"},{"name":"l1i","topo":"core"},{"name":"l2","topo":"mo= dule"},{"name":"l3","topo":"die"}]}' + -machine smp-cache=3Dcache ERST =20 DEF("M", HAS_ARG, QEMU_OPTION_M, @@ -5871,6 +5880,55 @@ SRST :: =20 (qemu) qom-set /objects/iothread1 poll-max-ns 100000 + + ``-object '{"qom-type":"smp-cache","id":id,"caches":[{"name":cache_nam= e,"topo":cache_topo}]}'`` + Create an smp-cache object that configures machine's cache + property. Currently, cache property only include cache topology + level. + + This option must be written in JSON format to support JSON list. + + The ``caches`` parameter accepts a list of cache property in JSON + format. + + A list element requires the cache name to be specified in the + ``name`` parameter (currently ``l1d``, ``l1i``, ``l2`` and ``l3`` + are supported). ``topo`` parameter accepts CPU topology levels + including ``thread``, ``core``, ``module``, ``cluster``, ``die``, + ``socket``, ``book``, ``drawer`` and ``default``. The ``topo`` + parameter indicates CPUs winthin the same CPU topology container + are sharing the same cache. + + Some machines may have their own cache topology model, and this + object may override the machine-specific cache topology setting + by specifying smp-cache object in the -machine. When specifying + the cache topology level of ``default``, it will honor the default + machine-specific cache topology setting. For other topology levels, + they will override the default setting. + + An example list of caches to configure the cache model (l1d cache + per core, l1i cache per core, l2 cache per module and l3 cache per + socket) supported by PC machine might look like: + + :: + + { + "caches": [ + { "name": "l1d", "topo": "core" }, + { "name": "l1i", "topo": "core" }, + { "name": "l2", "topo": "module" }, + { "name": "l3", "topo": "socket" }, + ] + } + + An example smp-cache object would look like:() + + .. parsed-literal:: + + # |qemu_system| \\ + ... \\ + -object '{"qom-type":"smp-cache","id":id,"caches":[{"name= ":cache_name,"topo":cache_topo}]}' \\ + ... ERST =20 =20 --=20 2.34.1