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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4256af557fesm161952135e9.11.2024.07.01.09.07.46 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Jul 2024 09:07:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1719850067; x=1720454867; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=jDxsxwb6wke90AJTR7bX+v27HwUxef5Wp/hVnhRyzbY=; b=WVRt26Jwrr5RVBjnVcHP0r2HRnMgK2xzX66Hw+dlMB3IGXxebtC86e7NVjudUe7nP/ DBBgSvCsE7GBCOM3r8q1er3p7KkMzLeeHOUH1VImAo2eNVGvd40Uyt416Cz7+DMCbOZR i0yrJNBpnMsuPCTdZVtfqKDy5hKBNnojlrNwoqNaww0C/TIyV4jZxW58QpTZa1anXalj njdiLfGAwh58q/ymBobhuw7DefXyvZ7tvhHh4Igd+1RnYu6KT4fC8VDcQiZXb2Oi8LhI NTaMVYWw66OwhfPcrOAVcOAK/bOhTn5renqIzfdIPiOJCHzotAxbTvyWF4vi1MOQsBYn 3tWw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1719850067; x=1720454867; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jDxsxwb6wke90AJTR7bX+v27HwUxef5Wp/hVnhRyzbY=; b=bcR8am2+50IGCXHVGnNfgEwFODTBu4hlR43cReDAqAgbqSfypPaD2aomcrxceGoKr+ XPCRa03vkL4g1xvcWLfvewxLclGxAtk7BzNV9vGh41KlgaavSvdkt//m93tgluXPb8qB cmoSGukTjq93UiCp02w94qXbfH4pYO/9mvGef2AyomDaRvk4nT9JYKYlq9GTqfkW9/BK itRKEQjNuKJ1TpDWP0Ty5vyLKZ3SRKyQozzX2p/5JS/TaY7W3c27ykS9vro6Sg4Il6ij G6vp4tNw5149jXoPwz4Eu7NViCC0IyK2XF5l2f5NHCef0aSWlowGw3D4fx8iz0QmTTYQ 7H2g== X-Gm-Message-State: AOJu0Yz8McT3TIXNe+DEgqgV3Sr++6QObkqlb3Fd2BwdNjXIx9vPIN2c qG5TGm3Ywfx1hcyeyLxwGJo21PjTfb1MOAN9yONDdoG2zAAIXIh+xey2Yy5HGmije4LQCD5F0KR gL9E= X-Google-Smtp-Source: AGHT+IGsuKXI3YaXResEN87ED5WxbotncR7N7Zq1ktyaNgcBXHIXtK2IWJ9jKerW5exS0q3GhioWyQ== X-Received: by 2002:a05:600c:6a8d:b0:425:77b4:366d with SMTP id 5b1f17b1804b1-4257a02f3f6mr41316475e9.11.1719850067025; Mon, 01 Jul 2024 09:07:47 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 29/29] tests/qtest: Ensure STM32L4x5 EXTI state is correct at the end of QTests Date: Mon, 1 Jul 2024 17:07:29 +0100 Message-Id: <20240701160729.1910763-30-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240701160729.1910763-1-peter.maydell@linaro.org> References: <20240701160729.1910763-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1719850184657100001 From: In=C3=A8s Varhol EXTI's new field `irq_levels` tracks irq levels between tests when using `global_qtest`. This happens in `stm32l4x5_exti-test.c`, `stm32l4x5_syscfg-test.c` and `stm32l4x5_gpio-test.c` (`dm163.c` doesn't use `global_qtest`). To ensure that `irq_levels` has the same value before and after each QTest, this commit toggles back the irq lines that were changed at the end of each problematic test. Most QTests were already doing this. Signed-off-by: In=C3=A8s Varhol Message-id: 20240629110800.539969-3-ines.varhol@telecom-paris.fr Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- tests/qtest/stm32l4x5_exti-test.c | 8 ++++++++ tests/qtest/stm32l4x5_syscfg-test.c | 2 +- 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/tests/qtest/stm32l4x5_exti-test.c b/tests/qtest/stm32l4x5_exti= -test.c index 7092860b9b7..7e39c992fd3 100644 --- a/tests/qtest/stm32l4x5_exti-test.c +++ b/tests/qtest/stm32l4x5_exti-test.c @@ -448,6 +448,9 @@ static void test_masked_interrupt(void) g_assert_cmphex(exti_readl(EXTI_PR1), =3D=3D, 0x00000000); /* Check that the interrupt isn't pending in NVIC */ g_assert_false(check_nvic_pending(EXTI1_IRQ)); + + /* Clean EXTI */ + exti_set_irq(1, 0); } =20 static void test_interrupt(void) @@ -498,6 +501,9 @@ static void test_interrupt(void) /* Clean NVIC */ unpend_nvic_irq(EXTI1_IRQ); g_assert_false(check_nvic_pending(EXTI1_IRQ)); + + /* Clean EXTI */ + exti_set_irq(1, 0); } =20 static void test_orred_interrupts(void) @@ -531,6 +537,8 @@ static void test_orred_interrupts(void) =20 unpend_nvic_irq(EXTI5_9_IRQ); g_assert_false(check_nvic_pending(EXTI5_9_IRQ)); + + exti_set_irq(i, 0); } } =20 diff --git a/tests/qtest/stm32l4x5_syscfg-test.c b/tests/qtest/stm32l4x5_sy= scfg-test.c index 1cdf8f05c80..258417cd889 100644 --- a/tests/qtest/stm32l4x5_syscfg-test.c +++ b/tests/qtest/stm32l4x5_syscfg-test.c @@ -221,10 +221,10 @@ static void test_interrupt(void) g_assert_true(get_irq(1)); =20 /* Clean the test */ - syscfg_writel(SYSCFG_EXTICR1, 0x00000000); syscfg_set_irq(0, 0); /* irq 15 is high at reset because GPIOA15 is high at reset */ syscfg_set_irq(17, 0); + syscfg_writel(SYSCFG_EXTICR1, 0x00000000); } =20 static void test_irq_pin_multiplexer(void) --=20 2.34.1