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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4256af557fesm161952135e9.11.2024.07.01.09.07.42 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Jul 2024 09:07:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1719850063; x=1720454863; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=MZkBdG186zLNGmCWvbcnLg3ZsyZ6IKvGgCf1O/oJF1E=; b=s6t9vnvI1FzACPzi1qAqgdqz11XABJwrFwo3RsOPEh5C5871Kuiac9B7gqPdfPiF5P uqMZjnnVL3cmMY43LEvc8rzj/fLIEJBp9oNKgz963chLJeklfqHUwKmBpTqaJIoKXSP3 CkkhX2OSPju9WwT0RqEngb+EEE+MPhQRzQaOkrzlfE21mQQIwmfmpH8FcrJkQLvWxyrj Y1ccKJ2xoXN8HRDw8G1VgcIw1M3O5Ni0PemX/yEIhBhdZmzTE/hh054dsghE3y5Clay1 nNkasULBv4JqjPX4VnGJYyVWRRw8/8q+g2vKhh9Rjk/UeC3QIWOhptVDSPNWrwh4MxTi K+mA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1719850063; x=1720454863; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MZkBdG186zLNGmCWvbcnLg3ZsyZ6IKvGgCf1O/oJF1E=; b=bCuMtYf1vgyvprM1kqPvbm5F1pdG2LX711QlnRqlTxOWHHOaUc6dLvJR9lJZ6/qpOg 8Sdg3kTaaES8ioNrNAmEzhGGBoaoCCL6pIjksva/Ll8IfAlooQECGsUA8drafgoUm7Se qzlp6XyFgvtL+Xhlts24rwFwI+IyvQbV/1ExpziJJu3J3UNeg+5k+/+NcK23KGoC9+6R lJbldNr5lGVfuS2OBF60ugsEnFPNy0CBWe8O2om/2wS9vOmnOxnqsr+cu04nhOhlS6Wg FhaGfQGLFlknbtWs4mRtTCBIF8PbfN3j03OQidLy9Cxoysk0rX7ZbBAP0kMXYh6xPNfc PEew== X-Gm-Message-State: AOJu0Ywp3kCZxyF9Aag2nT3S3EMUY9W7a18aV4x45CuHfLHfPv6nvBVx +QhlnyfhpyejCPqBt1OC6obilPm/3CRvOjtIc2WKfef6ibesc8t16vEFY7ZhALb4JpEW/ceoCQw kTgA= X-Google-Smtp-Source: AGHT+IE0xHH9zpwnjVu69hFbEROVa5u8NIr23rgrLhhQFbDnOJ37sFuccu1VuD13YCY+HBynsJuIlg== X-Received: by 2002:a2e:beaa:0:b0:2ec:5668:3b93 with SMTP id 38308e7fff4ca-2ee5e393845mr55492611fa.12.1719850062557; Mon, 01 Jul 2024 09:07:42 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 24/29] hw/misc/zynq_slcr: Add boot-mode property Date: Mon, 1 Jul 2024 17:07:24 +0100 Message-Id: <20240701160729.1910763-25-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240701160729.1910763-1-peter.maydell@linaro.org> References: <20240701160729.1910763-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::233; envelope-from=peter.maydell@linaro.org; helo=mail-lj1-x233.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1719850383872100001 Content-Type: text/plain; charset="utf-8" From: Sai Pavan Boddu boot-mode property sets user values into BOOT_MODE register, on hardware these are derived from board switches. Signed-off-by: Sai Pavan Boddu Reviewed-by: Edgar E. Iglesias Reviewed-by: Francisco Iglesias Message-id: 20240621125906.1300995-2-sai.pavan.boddu@amd.com Signed-off-by: Peter Maydell --- hw/misc/zynq_slcr.c | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/hw/misc/zynq_slcr.c b/hw/misc/zynq_slcr.c index 3412ff099ea..ad814c3a79b 100644 --- a/hw/misc/zynq_slcr.c +++ b/hw/misc/zynq_slcr.c @@ -24,6 +24,8 @@ #include "hw/registerfields.h" #include "hw/qdev-clock.h" #include "qom/object.h" +#include "hw/qdev-properties.h" +#include "qapi/error.h" =20 #ifndef ZYNQ_SLCR_ERR_DEBUG #define ZYNQ_SLCR_ERR_DEBUG 0 @@ -121,6 +123,7 @@ REG32(RST_REASON, 0x250) =20 REG32(REBOOT_STATUS, 0x258) REG32(BOOT_MODE, 0x25c) + FIELD(BOOT_MODE, BOOT_MODE, 0, 4) =20 REG32(APU_CTRL, 0x300) REG32(WDT_CLK_SEL, 0x304) @@ -195,6 +198,7 @@ struct ZynqSLCRState { Clock *ps_clk; Clock *uart0_ref_clk; Clock *uart1_ref_clk; + uint8_t boot_mode; }; =20 /* @@ -371,7 +375,7 @@ static void zynq_slcr_reset_init(Object *obj, ResetType= type) s->regs[R_FPGA_RST_CTRL] =3D 0x01F33F0F; s->regs[R_RST_REASON] =3D 0x00000040; =20 - s->regs[R_BOOT_MODE] =3D 0x00000001; + s->regs[R_BOOT_MODE] =3D s->boot_mode & R_BOOT_MODE_BOOT_MODE_MAS= K; =20 /* 0x700 - 0x7D4 */ for (i =3D 0; i < 54; i++) { @@ -588,6 +592,15 @@ static const ClockPortInitArray zynq_slcr_clocks =3D { QDEV_CLOCK_END }; =20 +static void zynq_slcr_realize(DeviceState *dev, Error **errp) +{ + ZynqSLCRState *s =3D ZYNQ_SLCR(dev); + + if (s->boot_mode > 0xF) { + error_setg(errp, "Invalid boot mode %d specified", s->boot_mode); + } +} + static void zynq_slcr_init(Object *obj) { ZynqSLCRState *s =3D ZYNQ_SLCR(obj); @@ -610,15 +623,22 @@ static const VMStateDescription vmstate_zynq_slcr =3D= { } }; =20 +static Property zynq_slcr_props[] =3D { + DEFINE_PROP_UINT8("boot-mode", ZynqSLCRState, boot_mode, 1), + DEFINE_PROP_END_OF_LIST(), +}; + static void zynq_slcr_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); ResettableClass *rc =3D RESETTABLE_CLASS(klass); =20 dc->vmsd =3D &vmstate_zynq_slcr; + dc->realize =3D zynq_slcr_realize; rc->phases.enter =3D zynq_slcr_reset_init; rc->phases.hold =3D zynq_slcr_reset_hold; rc->phases.exit =3D zynq_slcr_reset_exit; + device_class_set_props(dc, zynq_slcr_props); } =20 static const TypeInfo zynq_slcr_info =3D { --=20 2.34.1