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[174.21.76.141]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2c91d3e7e4bsm5115641a91.52.2024.06.30.12.01.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Jun 2024 12:01:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1719774063; x=1720378863; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=RVOFvPwsyl4QfxgYtVSSFj0skJQCOvZiNxR84pYswu0=; b=Akqf+zbC/mCYhJHZ/IYzpXhBzF4xKDKxcFh9JmFTV/uykanKQSajOoo6O+c9XkbjD6 AUI4PISNR6ogigq/Vi60YCqde3qCltTaqPHvYSm5Wj3T7NnoPvipZrVDNovO8ew7wgnB MEkPY2BI5YSOOv/X4dj0fxEBO1uZjdld9veUEOW/fcfbYfZv7h8myTTuT1J/gtodn182 LHcDuWLCyVK5F9mc81asMPcAZ3TzxVjn3xJaaa0Ou9dB+gHYy2X7whV2i7oXqjVJt0c6 aCJjKdF/mxKnms4op2lQKeVFolsbK4dgmYgL5cc2qSth2Izuy7TbB+itPpi0+p3OpyTB PoZg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1719774063; x=1720378863; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RVOFvPwsyl4QfxgYtVSSFj0skJQCOvZiNxR84pYswu0=; b=tbkWHTtJNQ3gg5AL+p+FQo9WiglSW3zEzfhCN9hiHSdHBciI0694yDkh0pJarpFSNG 7JAgjz5lb8w+ToIu5o0Vi3j9uhz9ucvujuUeX9Rtfjbn+ePWDRRAdOE3xQduSOEXpJ+Q JS0qRwrkt26aaEoascAyiCYdoFL8NNkKQbUp2Vf4thavrRh1An48f7OrFDsTp+f7O9cG P5aW4P/4yyfuVWhmPV4a0QmLg0nH72w49vI6VtrVC/IiCHaxYisgcPsAN7eFROTDxCCA BVUlqXp0wFLimzSiHFQl2SljVYFYelCCp8w/bT8aJn7rF8ytvKPcVBRBrgdaLonq2Sr4 cr0g== X-Gm-Message-State: AOJu0Ywc9MqEDa8s1Rq92olKWfEe0i4Q6/GMntZRu62WbEy9O1eanaSv gj+2HH0IP8GtXbeuPMCUKsrkP+lCWLCjXj2vTzYyuo7qqzZM1wKZPrPsSBrRQzWGLN8x9cWA4AL Z X-Google-Smtp-Source: AGHT+IHA7EAD2BcPbLOszhLP6OoRn2JyUpvo96A5Uk5LyADv0Efa7Q+vf8tGolXYGn9c94tdtTdkyQ== X-Received: by 2002:a05:6358:9486:b0:1a6:84aa:13f with SMTP id e5c5f4694b2df-1a6acf39bafmr430163455d.24.1719774062730; Sun, 30 Jun 2024 12:01:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: akihiko.odaki@daynix.com, alex.bennee@linaro.org, qemu-arm@nongnu.org Subject: [PATCH v4 11/14] tests/tcg/arm: Manually register allocate half-precision numbers Date: Sun, 30 Jun 2024 12:00:47 -0700 Message-Id: <20240630190050.160642-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240630190050.160642-1-richard.henderson@linaro.org> References: <20240630190050.160642-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::c2b; envelope-from=richard.henderson@linaro.org; helo=mail-oo1-xc2b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1719774293516100004 Content-Type: text/plain; charset="utf-8" From: Akihiko Odaki Clang does not allow specifying an integer as the value of a single precision register. Explicitly move value from a general register. Signed-off-by: Akihiko Odaki [rth: Use one single inline asm block.] Signed-off-by: Richard Henderson --- tests/tcg/arm/fcvt.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/tests/tcg/arm/fcvt.c b/tests/tcg/arm/fcvt.c index 157790e679..d8c61cd29f 100644 --- a/tests/tcg/arm/fcvt.c +++ b/tests/tcg/arm/fcvt.c @@ -355,7 +355,12 @@ static void convert_half_to_single(void) =20 print_half_number(i, input); #if defined(__arm__) - asm("vcvtb.f32.f16 %0, %1" : "=3Dw" (output) : "x" ((uint32_t)inpu= t)); + /* + * Clang refuses to allocate an integer to a fp register. + * Perform the move from a general register by hand. + */ + asm("vmov %0, %1\n\t" + "vcvtb.f32.f16 %0, %0" : "=3Dw" (output) : "r" (input)); #else asm("fcvt %s0, %h1" : "=3Dw" (output) : "w" (input)); #endif --=20 2.34.1