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([2804:7f0:b401:391e:3e7c:3fff:fe7a:e83b]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-72c6b2a16cdsm423932a12.46.2024.06.27.22.21.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Jun 2024 22:21:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1719552069; x=1720156869; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=iNGHLZ6SUmkXQCpzg0N2HSo1zlyebo9gy5r+WIIkQrU=; b=WLqVvAUD6sBfoVE7YMegGq8BsoFUW11o0aW9w1WdPXnrrj1QHfHE9Lea8gfnxiosKu AYB98uy3GUV/KyUDQRlmgumSePeh78NAByGQYIkh5H9Ddb9bgqQR6cqacFiu0hOf3s9I RzwtLh5WbT7eVIQewTbCBS5L1vhQ02BvNEfCkICVhEpczc4gM/oykQ1kHb5xbbhfFZES ubdRB01/taIgpdU6+yGXkVP+gYQJCNAI5lEnWLlaHhh+dNimaIvbjuX4qk64oYpo7NI/ 99oI5MYnjzLxj4Di5b9HsuaQdVXlNCc7ZieU5bRLqHgYnvBKNdTQGZAELMnwu3Ot7Vit +uuA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1719552069; x=1720156869; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=iNGHLZ6SUmkXQCpzg0N2HSo1zlyebo9gy5r+WIIkQrU=; b=UbrOZ9pf2GEfOzvRpzkLE521p7eBUUwGlwC4fdpnr+GSdSXH0qUF2EVcbJwmFZnr2d mMeG28UF5aultIbr5j9AhsMBfwAQQ70yf25gFK5NhCrJAbkoHA0dyK5vvaK/JgX6VCd5 pMh5xKuzCpPtnuzHJ4RrIS62OHRo1Sx9of6EidIAYUkwobSuxCUGYI/Lp45prJq8lPbv WQA7Ky5x9YHAaeIlsXlwXof96XDCfr6Yk3vnk0QMZPyJBJiO/2TdZFFPDwomox57dOhP 3pU3/FR5idhkxubEE0t7HZ/iPU6d0iCBLPeE4b4gd3gO3AM/ZEgZCEPoHwgk9LiQ3PkJ Jr+g== X-Gm-Message-State: AOJu0YwIXuvTuRH9nKF6Ur6lTVJCeS1bvjWKP1fqmqp0Pmq/Vn1s2KVQ xzvSAOV5+BJjOYjq0mKdtBnfgTOXfYUokTIIXZ+d6/vTziaEfOoyEiUd0GiT1snvscQ97IjA2hx 9 X-Google-Smtp-Source: AGHT+IGl7B2C5M3TIVp6fCWHXjk6PMBdWhepYrHRI2A8nCAsrhhToN6T3mBhUlhkvtboWDhvhZQEjQ== X-Received: by 2002:a05:6870:c1d2:b0:254:a8ec:306f with SMTP id 586e51a60fabf-25d0191bef2mr15450620fac.43.1719552068490; Thu, 27 Jun 2024 22:21:08 -0700 (PDT) From: Gustavo Romero To: qemu-devel@nongnu.org, philmd@linaro.org, alex.bennee@linaro.org, richard.henderson@linaro.org Cc: peter.maydell@linaro.org, gustavo.romero@linaro.org Subject: [PATCH v6 05/11] target/arm: Make some MTE helpers widely available Date: Fri, 28 Jun 2024 05:08:44 +0000 Message-Id: <20240628050850.536447-6-gustavo.romero@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240628050850.536447-1-gustavo.romero@linaro.org> References: <20240628050850.536447-1-gustavo.romero@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::330; envelope-from=gustavo.romero@linaro.org; helo=mail-ot1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1719552137627100005 Make the MTE helpers allocation_tag_mem_probe, load_tag1, and store_tag1 available to other subsystems. Signed-off-by: Gustavo Romero Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/tcg/mte_helper.c | 45 ++++--------------------- target/arm/tcg/mte_helper.h | 66 +++++++++++++++++++++++++++++++++++++ 2 files changed, 73 insertions(+), 38 deletions(-) create mode 100644 target/arm/tcg/mte_helper.h diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c index a50d576294..9d2ba287ee 100644 --- a/target/arm/tcg/mte_helper.c +++ b/target/arm/tcg/mte_helper.c @@ -29,6 +29,7 @@ #include "hw/core/tcg-cpu-ops.h" #include "qapi/error.h" #include "qemu/guest-random.h" +#include "mte_helper.h" =20 =20 static int choose_nonexcluded_tag(int tag, int offset, uint16_t exclude) @@ -50,42 +51,10 @@ static int choose_nonexcluded_tag(int tag, int offset, = uint16_t exclude) return tag; } =20 -/** - * allocation_tag_mem_probe: - * @env: the cpu environment - * @ptr_mmu_idx: the addressing regime to use for the virtual address - * @ptr: the virtual address for which to look up tag memory - * @ptr_access: the access to use for the virtual address - * @ptr_size: the number of bytes in the normal memory access - * @tag_access: the access to use for the tag memory - * @probe: true to merely probe, never taking an exception - * @ra: the return address for exception handling - * - * Our tag memory is formatted as a sequence of little-endian nibbles. - * That is, the byte at (addr >> (LOG2_TAG_GRANULE + 1)) contains two - * tags, with the tag at [3:0] for the lower addr and the tag at [7:4] - * for the higher addr. - * - * Here, resolve the physical address from the virtual address, and return - * a pointer to the corresponding tag byte. - * - * If there is no tag storage corresponding to @ptr, return NULL. - * - * If the page is inaccessible for @ptr_access, or has a watchpoint, there= are - * three options: - * (1) probe =3D true, ra =3D 0 : pure probe -- we return NULL if the page= is not - * accessible, and do not take watchpoint traps. The calling code must - * handle those cases in the right priority compared to MTE traps. - * (2) probe =3D false, ra =3D 0 : probe, no fault expected -- the caller = guarantees - * that the page is going to be accessible. We will take watchpoint tr= aps. - * (3) probe =3D false, ra !=3D 0 : non-probe -- we will take both memory = access - * traps and watchpoint traps. - * (probe =3D true, ra !=3D 0 is invalid and will assert.) - */ -static uint8_t *allocation_tag_mem_probe(CPUARMState *env, int ptr_mmu_idx, - uint64_t ptr, MMUAccessType ptr_a= ccess, - int ptr_size, MMUAccessType tag_a= ccess, - bool probe, uintptr_t ra) +uint8_t *allocation_tag_mem_probe(CPUARMState *env, int ptr_mmu_idx, + uint64_t ptr, MMUAccessType ptr_access, + int ptr_size, MMUAccessType tag_access, + bool probe, uintptr_t ra) { #ifdef CONFIG_USER_ONLY uint64_t clean_ptr =3D useronly_clean_ptr(ptr); @@ -287,7 +256,7 @@ uint64_t HELPER(addsubg)(CPUARMState *env, uint64_t ptr, return address_with_allocation_tag(ptr + offset, rtag); } =20 -static int load_tag1(uint64_t ptr, uint8_t *mem) +int load_tag1(uint64_t ptr, uint8_t *mem) { int ofs =3D extract32(ptr, LOG2_TAG_GRANULE, 1) * 4; return extract32(*mem, ofs, 4); @@ -321,7 +290,7 @@ static void check_tag_aligned(CPUARMState *env, uint64_= t ptr, uintptr_t ra) } =20 /* For use in a non-parallel context, store to the given nibble. */ -static void store_tag1(uint64_t ptr, uint8_t *mem, int tag) +void store_tag1(uint64_t ptr, uint8_t *mem, int tag) { int ofs =3D extract32(ptr, LOG2_TAG_GRANULE, 1) * 4; *mem =3D deposit32(*mem, ofs, 4, tag); diff --git a/target/arm/tcg/mte_helper.h b/target/arm/tcg/mte_helper.h new file mode 100644 index 0000000000..1f471fb69b --- /dev/null +++ b/target/arm/tcg/mte_helper.h @@ -0,0 +1,66 @@ +/* + * ARM MemTag operation helpers. + * + * This code is licensed under the GNU GPL v2 or later. + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ + +#ifndef TARGET_ARM_MTE_H +#define TARGET_ARM_MTE_H + +#include "exec/mmu-access-type.h" + +/** + * allocation_tag_mem_probe: + * @env: the cpu environment + * @ptr_mmu_idx: the addressing regime to use for the virtual address + * @ptr: the virtual address for which to look up tag memory + * @ptr_access: the access to use for the virtual address + * @ptr_size: the number of bytes in the normal memory access + * @tag_access: the access to use for the tag memory + * @probe: true to merely probe, never taking an exception + * @ra: the return address for exception handling + * + * Our tag memory is formatted as a sequence of little-endian nibbles. + * That is, the byte at (addr >> (LOG2_TAG_GRANULE + 1)) contains two + * tags, with the tag at [3:0] for the lower addr and the tag at [7:4] + * for the higher addr. + * + * Here, resolve the physical address from the virtual address, and return + * a pointer to the corresponding tag byte. + * + * If there is no tag storage corresponding to @ptr, return NULL. + * + * If the page is inaccessible for @ptr_access, or has a watchpoint, there= are + * three options: + * (1) probe =3D true, ra =3D 0 : pure probe -- we return NULL if the page= is not + * accessible, and do not take watchpoint traps. The calling code must + * handle those cases in the right priority compared to MTE traps. + * (2) probe =3D false, ra =3D 0 : probe, no fault expected -- the caller = guarantees + * that the page is going to be accessible. We will take watchpoint tr= aps. + * (3) probe =3D false, ra !=3D 0 : non-probe -- we will take both memory = access + * traps and watchpoint traps. + * (probe =3D true, ra !=3D 0 is invalid and will assert.) + */ +uint8_t *allocation_tag_mem_probe(CPUARMState *env, int ptr_mmu_idx, + uint64_t ptr, MMUAccessType ptr_access, + int ptr_size, MMUAccessType tag_access, + bool probe, uintptr_t ra); + +/** + * load_tag1 - Load 1 tag (nibble) from byte + * @ptr: The tagged address + * @mem: The tag address (packed, 2 tags in byte) + */ +int load_tag1(uint64_t ptr, uint8_t *mem); + +/** + * store_tag1 - Store 1 tag (nibble) into byte + * @ptr: The tagged address + * @mem: The tag address (packed, 2 tags in byte) + * @tag: The tag to be stored in the nibble + */ +void store_tag1(uint64_t ptr, uint8_t *mem, int tag); + +#endif /* TARGET_ARM_MTE_H */ --=20 2.34.1