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[2403:580b:97e8:0:82ce:f179:8a79:69f4]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-706b4a07326sm932431b3a.111.2024.06.27.03.02.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Jun 2024 03:02:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1719482549; x=1720087349; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=AnEaxExSxNmbwr/9W4/pvVWPb9oM7FgPkjyis6ytKNc=; b=biI5mAMqkRWZaNfd1jCBIwTbacjhZUhpR6QZFwSUaxxo6WHX2v8kVoVtTRl7NstTZd gVs9PhFSywjWjIsZ7YFmoocjWFsrGAGPMo7tajPWIXDVFE/hk3vZlZ0OWguQmY1Svbvj N1sWsQKPXWvwaBXbr0O8qu7PeL+H5G5/KCB6adzb6crrV9iidQWlCeftolMtsOZBVgOF M6zvGJe3GJ2F3IaaXYuBxmPcvaqh00vPJP6sz2AWK9O9RfnViiQ/0DBoSgM+EyJHfqpz bYq59I+JTWK0lN6BR0bN5734ke/LJBJPR0K6/GyhsfOLC6hDM33x/KwSrIM1jsuiXiKN AgIQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1719482549; x=1720087349; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=AnEaxExSxNmbwr/9W4/pvVWPb9oM7FgPkjyis6ytKNc=; b=Pyh5MrdDzQS23exAuAKh2WsYyWABpiNW96PxkMZc9xM+tmny3LEAFLAfRhZnOLgPLE sIFQQOjj58M8UI/vQ+KN+cHrEcnFomfWJo0IACnfetOULP2i3q5TYkJSvIVU5BJ0af6O vtdzB32VbiXbdzkxnmi9enpW18M6B7ELoEBuDNjVQaWp4lMqQpTzKJOsG5ImzASMSNpE aP/pYh9DD8tDTAX3qOZsPuPUaVRNCeGgZo2wLJxsut4miP98dYt+Y5lePTvWhuEwmp/W jf7F6WTSHpYJgCGH3WN7pt27TL4RVbZ3k5Nk20QRaxi3Zo6fXD56vQEdUrdcPI19aU+t L3Kg== X-Gm-Message-State: AOJu0YwANfCzHw8gg1iam8QY+Rx9DDSzlrdJxI+2ce3vsU5TdFmwqJmv 316XgPLpftrWbwyIyfjdTEgKOCF4sZjdVXA0TVe0dT3d3ujL8IPvF8D1ubmH X-Google-Smtp-Source: AGHT+IHtqf5Txsppm8q8DMszDbNclDzwwb1/Hc2PWeJNHIaTPYrKAIPIU/AD7wgGseGslDKWqnAPOA== X-Received: by 2002:aa7:8611:0:b0:706:375e:220d with SMTP id d2e1a72fcca58-706746fa56cmr12021869b3a.30.1719482549185; Thu, 27 Jun 2024 03:02:29 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Frank Chang , Jerry Zhang Jian , Max Chou , Alistair Francis , Daniel Henrique Barboza Subject: [PULL 26/32] target/riscv: Add MISA extension implied rules Date: Thu, 27 Jun 2024 20:00:47 +1000 Message-ID: <20240627100053.150937-27-alistair.francis@wdc.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240627100053.150937-1-alistair.francis@wdc.com> References: <20240627100053.150937-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=alistair23@gmail.com; helo=mail-pf1-x434.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1719482669411100001 Content-Type: text/plain; charset="utf-8" From: Frank Chang Add MISA extension implied rules to enable the implied extensions of MISA recursively. Signed-off-by: Frank Chang Reviewed-by: Jerry Zhang Jian Tested-by: Max Chou Reviewed-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza Message-ID: <20240625114629.27793-4-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 50 +++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 49 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 7b071ade04..b463bd8370 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -2250,8 +2250,56 @@ RISCVCPUProfile *riscv_profiles[] =3D { NULL, }; =20 +static RISCVCPUImpliedExtsRule RVA_IMPLIED =3D { + .is_misa =3D true, + .ext =3D RVA, + .implied_multi_exts =3D { + CPU_CFG_OFFSET(ext_zalrsc), CPU_CFG_OFFSET(ext_zaamo), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + +static RISCVCPUImpliedExtsRule RVD_IMPLIED =3D { + .is_misa =3D true, + .ext =3D RVD, + .implied_misa_exts =3D RVF, + .implied_multi_exts =3D { RISCV_IMPLIED_EXTS_RULE_END }, +}; + +static RISCVCPUImpliedExtsRule RVF_IMPLIED =3D { + .is_misa =3D true, + .ext =3D RVF, + .implied_multi_exts =3D { + CPU_CFG_OFFSET(ext_zicsr), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + +static RISCVCPUImpliedExtsRule RVM_IMPLIED =3D { + .is_misa =3D true, + .ext =3D RVM, + .implied_multi_exts =3D { + CPU_CFG_OFFSET(ext_zmmul), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + +static RISCVCPUImpliedExtsRule RVV_IMPLIED =3D { + .is_misa =3D true, + .ext =3D RVV, + .implied_multi_exts =3D { + CPU_CFG_OFFSET(ext_zve64d), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + RISCVCPUImpliedExtsRule *riscv_misa_ext_implied_rules[] =3D { - NULL + &RVA_IMPLIED, &RVD_IMPLIED, &RVF_IMPLIED, + &RVM_IMPLIED, &RVV_IMPLIED, NULL }; =20 RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[] =3D { --=20 2.45.2