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([2804:7f0:b401:391e:3e7c:3fff:fe7a:e83b]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-72748e8539fsm273045a12.66.2024.06.26.21.14.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Jun 2024 21:14:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1719461664; x=1720066464; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=yzx9s/7tqo4YbR/masBSAAi0+ITK6Y2yWNbJ1lluZfs=; b=n2OKgKnwsj7o8ULAcX5Wt07+06L0tKV2y38SEWEU/NlQiBx5rZy7HjaKDGUt128YsS Jj/rfIGcpargafGj9cbPhpuWNKM60tjGv+ro6FwxkiWsF2oiNx3ysiAa8OLNCcsTaqTY kqmmTb9dip6WvoJ8eL+E40ZFXn8Xv9ZgYbGSyyQOI8tdAldJS+zvM4uiSFMh1N9x22G3 5CxGgjbqg3CfWf9mxt9JNFBTTnr7YRguZD7C9CLrh1x3MJHnWqIftKD6opF0ZMFWWB1/ UVElZGKDEzGZgVNKFv+dh5MkevoIUPadCTvfjJg5GwS20LdD+GNf6cBl3qhvh1hOT7jp qGxg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1719461664; x=1720066464; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yzx9s/7tqo4YbR/masBSAAi0+ITK6Y2yWNbJ1lluZfs=; b=fcmybRtTz4T2HeVjAJ3JC+ImKGfPr60cfysqIX9P7TeavKDktCHLCRrKNeJY346jO4 OSs5qwzVeEpLnGtQaHtCHvTF8+vy72fu3hWXvdqv9TepGlCWfiXftu8Y9l6dw6ZeaBMo 4vcQJL8LwgsEil08U0HtQ1m9oGxsWQXxzuTghPLLYwzlae982jHjOVlWleekVDgiao6A OZR7KpeA0y2x7gltJigF4Xaa9J85e7nuyo6b7a+iAE81tybVPeV9XCKKV3skuHJFPIiZ 4eMVZjkUmozgK2yDfdY9Q8Mww1hWd+GBzG6atjw4QqtCTYoNwiBROX0Rt6yOAVXsIPoq aPEg== X-Gm-Message-State: AOJu0YzFrhb4jVBmUtxxhNYEkYKbw14C9+/Dc5YxiXXSPjeGAPUFw3NE ZLCEPTQxzjWofXLSXY94HNLSPZLsrX+aKkqMI9c9ZuXuDZw4zZejIegtFf7jrDzCWx0THEKsgjI HIA8= X-Google-Smtp-Source: AGHT+IEe5A0rqdIuCBbYgsmHsoqvfbkxFoJvtw3KKA8QMelJPRgRZTFd544b02cXOhIFF6WpxM2oGA== X-Received: by 2002:a05:6e02:214c:b0:375:aa46:4a30 with SMTP id e9e14a558f8ab-3763e0600f9mr184672505ab.23.1719461663656; Wed, 26 Jun 2024 21:14:23 -0700 (PDT) From: Gustavo Romero To: qemu-devel@nongnu.org, philmd@linaro.org, alex.bennee@linaro.org, richard.henderson@linaro.org Cc: peter.maydell@linaro.org, gustavo.romero@linaro.org Subject: [PATCH v5 6/9] target/arm: Factor out code for setting MTE TCF0 field Date: Thu, 27 Jun 2024 04:13:46 +0000 Message-Id: <20240627041349.356704-7-gustavo.romero@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240627041349.356704-1-gustavo.romero@linaro.org> References: <20240627041349.356704-1-gustavo.romero@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::12e; envelope-from=gustavo.romero@linaro.org; helo=mail-il1-x12e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1719461742123100001 Content-Type: text/plain; charset="utf-8" Factor out the code used for setting the MTE TCF0 field from the prctl code into a convenient function. Other subsystems, like gdbstub, need to set this field as well, so keep it as a separate function to avoid duplication and ensure consistency in how this field is set across the board. Signed-off-by: Gustavo Romero Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- linux-user/aarch64/meson.build | 2 ++ linux-user/aarch64/mte_user_helper.c | 34 ++++++++++++++++++++++++++++ linux-user/aarch64/mte_user_helper.h | 25 ++++++++++++++++++++ linux-user/aarch64/target_prctl.h | 22 ++---------------- 4 files changed, 63 insertions(+), 20 deletions(-) create mode 100644 linux-user/aarch64/mte_user_helper.c create mode 100644 linux-user/aarch64/mte_user_helper.h diff --git a/linux-user/aarch64/meson.build b/linux-user/aarch64/meson.build index 248c578d15..f75bb3cd75 100644 --- a/linux-user/aarch64/meson.build +++ b/linux-user/aarch64/meson.build @@ -9,3 +9,5 @@ vdso_le_inc =3D gen_vdso.process('vdso-le.so', extra_args: ['-r', '__kernel_rt_sigreturn']) =20 linux_user_ss.add(when: 'TARGET_AARCH64', if_true: [vdso_be_inc, vdso_le_i= nc]) + +linux_user_ss.add(when: 'TARGET_AARCH64', if_true: [files('mte_user_helper= .c')]) diff --git a/linux-user/aarch64/mte_user_helper.c b/linux-user/aarch64/mte_= user_helper.c new file mode 100644 index 0000000000..8be6deaf03 --- /dev/null +++ b/linux-user/aarch64/mte_user_helper.c @@ -0,0 +1,34 @@ +/* + * ARM MemTag convenience functions. + * + * This code is licensed under the GNU GPL v2 or later. + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ + +#include +#include "mte_user_helper.h" + +void arm_set_mte_tcf0(CPUArchState *env, abi_long value) +{ + /* + * Write PR_MTE_TCF to SCTLR_EL1[TCF0]. + * + * The kernel has a per-cpu configuration for the sysadmin, + * /sys/devices/system/cpu/cpu/mte_tcf_preferred, + * which qemu does not implement. + * + * Because there is no performance difference between the modes, and + * because SYNC is most useful for debugging MTE errors, choose SYNC + * as the preferred mode. With this preference, and the way the API + * uses only two bits, there is no way for the program to select + * ASYMM mode. + */ + unsigned tcf =3D 0; + if (value & PR_MTE_TCF_SYNC) { + tcf =3D 1; + } else if (value & PR_MTE_TCF_ASYNC) { + tcf =3D 2; + } + env->cp15.sctlr_el[1] =3D deposit64(env->cp15.sctlr_el[1], 38, 2, tcf); +} diff --git a/linux-user/aarch64/mte_user_helper.h b/linux-user/aarch64/mte_= user_helper.h new file mode 100644 index 0000000000..ee3f6b190a --- /dev/null +++ b/linux-user/aarch64/mte_user_helper.h @@ -0,0 +1,25 @@ +/* + * ARM MemTag convenience functions. + * + * This code is licensed under the GNU GPL v2 or later. + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ + +#ifndef AARCH64_MTE_USER_HELPER_H +#define AARCH64_MTE USER_HELPER_H + +#include "qemu/osdep.h" +#include "qemu.h" + +/** + * arm_set_mte_tcf0 - Set TCF0 field in SCTLR_EL1 register + * @env: The CPU environment + * @value: The value to be set for the Tag Check Fault in EL0 field. + * + * Only SYNC and ASYNC modes can be selected. If ASYMM mode is given, the = SYNC + * mode is selected instead. So, there is no way to set the ASYMM mode. + */ +void arm_set_mte_tcf0(CPUArchState *env, abi_long value); + +#endif /* AARCH64_MTE_USER_HELPER_H */ diff --git a/linux-user/aarch64/target_prctl.h b/linux-user/aarch64/target_= prctl.h index aa8e203c15..ed75b9e4b5 100644 --- a/linux-user/aarch64/target_prctl.h +++ b/linux-user/aarch64/target_prctl.h @@ -7,6 +7,7 @@ #define AARCH64_TARGET_PRCTL_H =20 #include "target/arm/cpu-features.h" +#include "mte_user_helper.h" =20 static abi_long do_prctl_sve_get_vl(CPUArchState *env) { @@ -173,26 +174,7 @@ static abi_long do_prctl_set_tagged_addr_ctrl(CPUArchS= tate *env, abi_long arg2) env->tagged_addr_enable =3D arg2 & PR_TAGGED_ADDR_ENABLE; =20 if (cpu_isar_feature(aa64_mte, cpu)) { - /* - * Write PR_MTE_TCF to SCTLR_EL1[TCF0]. - * - * The kernel has a per-cpu configuration for the sysadmin, - * /sys/devices/system/cpu/cpu/mte_tcf_preferred, - * which qemu does not implement. - * - * Because there is no performance difference between the modes, a= nd - * because SYNC is most useful for debugging MTE errors, choose SY= NC - * as the preferred mode. With this preference, and the way the A= PI - * uses only two bits, there is no way for the program to select - * ASYMM mode. - */ - unsigned tcf =3D 0; - if (arg2 & PR_MTE_TCF_SYNC) { - tcf =3D 1; - } else if (arg2 & PR_MTE_TCF_ASYNC) { - tcf =3D 2; - } - env->cp15.sctlr_el[1] =3D deposit64(env->cp15.sctlr_el[1], 38, 2, = tcf); + arm_set_mte_tcf0(env, arg2); =20 /* * Write PR_MTE_TAG to GCR_EL1[Exclude]. --=20 2.34.1