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Thu, 27 Jun 2024 06:58:20 -0700 (PDT) From: Akihiko Odaki Date: Thu, 27 Jun 2024 22:58:03 +0900 Subject: [PATCH v2 2/6] tests/tcg/aarch64: Fix test architecture specification MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240627-tcg-v2-2-1690a813348e@daynix.com> References: <20240627-tcg-v2-0-1690a813348e@daynix.com> In-Reply-To: <20240627-tcg-v2-0-1690a813348e@daynix.com> To: Peter Maydell , =?utf-8?q?Alex_Benn=C3=A9e?= , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Akihiko Odaki X-Mailer: b4 0.14-dev-fd6e3 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=2607:f8b0:4864:20::632; envelope-from=akihiko.odaki@daynix.com; helo=mail-pl1-x632.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @daynix-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1719496785273100009 sme-smopa-2.c requires sme-i16i64 but the compiler option used not to specify it. Instead, the extension was specified with the inline assembly, resulting in mixing assembly code targeting sme-i1664 and C code that does not target sme-i1664. clang version 18.1.6 does not support such mixing so properly specify the extension with the compiler option instead. Signed-off-by: Akihiko Odaki --- tests/tcg/aarch64/sme-smopa-2.c | 2 +- tests/tcg/aarch64/Makefile.target | 11 +++++++++-- 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/tests/tcg/aarch64/sme-smopa-2.c b/tests/tcg/aarch64/sme-smopa-= 2.c index c9f48c3bfca2..2c9707065992 100644 --- a/tests/tcg/aarch64/sme-smopa-2.c +++ b/tests/tcg/aarch64/sme-smopa-2.c @@ -14,7 +14,7 @@ int main() long svl; =20 /* Validate that we have a wide enough vector for 4 elements. */ - asm(".arch armv8-r+sme-i64\n\trdsvl %0, #1" : "=3Dr"(svl)); + asm("rdsvl %0, #1" : "=3Dr"(svl)); if (svl < 32) { return 0; } diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile= .target index 70d728ae9af7..ad99e0e3b198 100644 --- a/tests/tcg/aarch64/Makefile.target +++ b/tests/tcg/aarch64/Makefile.target @@ -27,7 +27,8 @@ config-cc.mak: Makefile $(call cc-option,-march=3Darmv8.5-a, CROSS_CC_HAS_ARMV8_= 5); \ $(call cc-option,-mbranch-protection=3Dstandard, CROSS_CC_HAS_ARMV8_= BTI); \ $(call cc-option,-march=3Darmv8.5-a+memtag, CROSS_CC_HAS_ARMV8_= MTE); \ - $(call cc-option,-Wa$(COMMA)-march=3Darmv9-a+sme, CROSS_AS_HAS_ARMV9_= SME)) 3> config-cc.mak + $(call cc-option,-Wa$(COMMA)-march=3Darmv9-a+sme, CROSS_AS_HAS_ARMV9_= SME); \ + $(call cc-option,-march=3Darmv9-a+sme-i16i64, CROSS_AS_HAS_ARMV9_= SME_I1664)) 3> config-cc.mak -include config-cc.mak =20 ifneq ($(CROSS_CC_HAS_ARMV8_2),) @@ -68,7 +69,13 @@ endif =20 # SME Tests ifneq ($(CROSS_AS_HAS_ARMV9_SME),) -AARCH64_TESTS +=3D sme-outprod1 sme-smopa-1 sme-smopa-2 +AARCH64_TESTS +=3D sme-outprod1 sme-smopa-1 +endif + +# SME I16I64 Tests +ifneq ($(CROSS_AS_HAS_ARMV9_SME_I1664),) +AARCH64_TESTS +=3D sme-smopa-2 +sme-smopa-2: CFLAGS +=3D -march=3Darmv9-a+sme-i16i64 endif =20 # System Registers Tests --=20 2.45.2