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Tsirkin" , =?utf-8?q?Alex_Benn=C3=A9e?= , Peter Xu , Fabiano Rosas , Paolo Bonzini , David Hildenbrand , Thomas Huth , Laurent Vivier Cc: qemu-devel@nongnu.org, qemu-block@nongnu.org, qemu-ppc@nongnu.org, Akihiko Odaki X-Mailer: b4 0.14-dev-fd6e3 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=2607:f8b0:4864:20::631; envelope-from=akihiko.odaki@daynix.com; helo=mail-pl1-x631.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @daynix-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1719495689584100003 A function pointer is sufficient for internal usage. Replacing qemu_irq with one fixes the leak of qemu_irq. Signed-off-by: Akihiko Odaki --- include/hw/ppc/mac_dbdma.h | 5 +++-- hw/ide/macio.c | 11 +++++++---- hw/misc/macio/mac_dbdma.c | 10 +++++----- 3 files changed, 15 insertions(+), 11 deletions(-) diff --git a/include/hw/ppc/mac_dbdma.h b/include/hw/ppc/mac_dbdma.h index 4a3f644516b3..1e1973c39580 100644 --- a/include/hw/ppc/mac_dbdma.h +++ b/include/hw/ppc/mac_dbdma.h @@ -32,6 +32,7 @@ typedef struct DBDMA_io DBDMA_io; =20 typedef void (*DBDMA_flush)(DBDMA_io *io); +typedef void (*DBDMA_irq)(DBDMA_io *io); typedef void (*DBDMA_rw)(DBDMA_io *io); typedef void (*DBDMA_end)(DBDMA_io *io); struct DBDMA_io { @@ -154,7 +155,7 @@ typedef struct dbdma_cmd { typedef struct DBDMA_channel { int channel; uint32_t regs[DBDMA_REGS]; - qemu_irq irq; + DBDMA_irq irq; DBDMA_io io; DBDMA_rw rw; DBDMA_flush flush; @@ -172,7 +173,7 @@ typedef struct DBDMAState DBDMAState; =20 /* Externally callable functions */ =20 -void DBDMA_register_channel(void *dbdma, int nchan, qemu_irq irq, +void DBDMA_register_channel(void *dbdma, int nchan, DBDMA_irq irq, DBDMA_rw rw, DBDMA_flush flush, void *opaque); void DBDMA_kick(DBDMAState *dbdma); diff --git a/hw/ide/macio.c b/hw/ide/macio.c index 9c96a857a7c1..425b670a52a9 100644 --- a/hw/ide/macio.c +++ b/hw/ide/macio.c @@ -427,9 +427,8 @@ static void macio_ide_realizefn(DeviceState *dev, Error= **errp) s->bus.dma =3D &s->dma; } =20 -static void pmac_irq(void *opaque, int n, int level) +static void pmac_irq(MACIOIDEState *s, int n, int level) { - MACIOIDEState *s =3D opaque; uint32_t mask =3D 0x80000000u >> n; =20 /* We need to reflect the IRQ state in the irq register */ @@ -446,6 +445,11 @@ static void pmac_irq(void *opaque, int n, int level) } } =20 +static void pmac_dma_irq(DBDMA_io *io) +{ + pmac_irq(io->opaque, 0, 1); +} + static void pmac_ide_irq(void *opaque, int n, int level) { pmac_irq(opaque, 1, level); @@ -461,7 +465,6 @@ static void macio_ide_initfn(Object *obj) sysbus_init_mmio(d, &s->mem); sysbus_init_irq(d, &s->real_ide_irq); sysbus_init_irq(d, &s->real_dma_irq); - s->dma_irq =3D qemu_allocate_irq(pmac_irq, s, 0); qdev_init_gpio_in_named_with_opaque(DEVICE(obj), pmac_ide_irq, s, NULL= , 1); =20 object_property_add_link(obj, "dbdma", TYPE_MAC_DBDMA, @@ -513,7 +516,7 @@ void macio_ide_init_drives(MACIOIDEState *s, DriveInfo = **hd_table) =20 void macio_ide_register_dma(MACIOIDEState *s) { - DBDMA_register_channel(s->dbdma, s->channel, s->dma_irq, + DBDMA_register_channel(s->dbdma, s->channel, pmac_dma_irq, pmac_ide_transfer, pmac_ide_flush, s); } =20 diff --git a/hw/misc/macio/mac_dbdma.c b/hw/misc/macio/mac_dbdma.c index 2a528ea08caf..3450105ad851 100644 --- a/hw/misc/macio/mac_dbdma.c +++ b/hw/misc/macio/mac_dbdma.c @@ -114,7 +114,7 @@ static void kill_channel(DBDMA_channel *ch) ch->regs[DBDMA_STATUS] |=3D DEAD; ch->regs[DBDMA_STATUS] &=3D ~ACTIVE; =20 - qemu_irq_raise(ch->irq); + ch->irq(&ch->io); } =20 static void conditional_interrupt(DBDMA_channel *ch) @@ -133,7 +133,7 @@ static void conditional_interrupt(DBDMA_channel *ch) case INTR_NEVER: /* don't interrupt */ return; case INTR_ALWAYS: /* always interrupt */ - qemu_irq_raise(ch->irq); + ch->irq(&ch->io); DBDMA_DPRINTFCH(ch, "%s: raise\n", __func__); return; } @@ -148,13 +148,13 @@ static void conditional_interrupt(DBDMA_channel *ch) switch(intr) { case INTR_IFSET: /* intr if condition bit is 1 */ if (cond) { - qemu_irq_raise(ch->irq); + ch->irq(&ch->io); DBDMA_DPRINTFCH(ch, "%s: raise\n", __func__); } return; case INTR_IFCLR: /* intr if condition bit is 0 */ if (!cond) { - qemu_irq_raise(ch->irq); + ch->irq(&ch->io); DBDMA_DPRINTFCH(ch, "%s: raise\n", __func__); } return; @@ -562,7 +562,7 @@ void DBDMA_kick(DBDMAState *dbdma) qemu_bh_schedule(dbdma->bh); } =20 -void DBDMA_register_channel(void *dbdma, int nchan, qemu_irq irq, +void DBDMA_register_channel(void *dbdma, int nchan, DBDMA_irq irq, DBDMA_rw rw, DBDMA_flush flush, void *opaque) { --=20 2.45.2