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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f9eb321d4esm79472325ad.67.2024.06.25.04.46.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Jun 2024 04:46:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1719316017; x=1719920817; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qax+N6zJMlHLL8gC9AsPWc/LtF/KqpVZ6WmTr4ImBMo=; b=ata3nTlee/w3ir7ewnAl6cB7MnTzX++7mFYn1UnKqVHNhvBY4gPHSbhkIyfdTDTYmJ sMojYzhCNV6KJEG5x81DoNCTQulSuVbX4rBZIrcr5ReopHGc9eNXue92zn0Yy36k9lRp Zfd37+ne3bqrq5GOs/DGclfqaEDJnKaves1ztz/+D9NPcHKgC7z3VcxzEagFNQGax1BG BDEeUq3q5yKvM4BN5rt0sjwKmKxFVqRibVZdg4rM1TDsoguMQMAjvJ07xhNzeu/2ejVe b+6jkxo78N768HQZQsR22ygt72ENIxbui7IWmf/106SQiFQGX3F/1Mh8RpP5JfldjlKO c9bA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1719316017; x=1719920817; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qax+N6zJMlHLL8gC9AsPWc/LtF/KqpVZ6WmTr4ImBMo=; b=hVfBllkTfm48KsWxoks86u+aXjzpBCf5eOINotldNmidoYlVM4bGqP6Do4Um9KYeHV NIPk25VPU411JAjMglvecup8Smpz4PQeTfa5xaHDnYBiOZO3XaMJ855Jo8FGtIlyS3Bl xglFcEhfFYVouPYFiKLLtMGAhMUKCK0dHCX3dptUrATUlexLKpxUImSTdXla1vZt6yAH 1qocxRyXXDUB21IE//w8FIjdXbTyu+jC0u481duZ/igbEf3sFKoYQQ8ud+/ikbv6on// TDKOOKGYjSxJsQW2zyFTuORFdp0aKDdsDk0JVYFLWrC/coTWeJOQYjGE6mJ85+oifrHl HHQg== X-Gm-Message-State: AOJu0YxGRTogKu67ZTY3kdlTJ4BFJxAX02obSCkVsfKiYegn/wdFsowa mDE/B1AndgXwo4s8/egRh25btaX+JAaQ/PbQz3ntMwC58OahRbyLvGuagRCJ3Yhs3ZyKCclTRhS Ge4WLWB6R/QNewqdJPS0J2YD1tzZyJtFjh2ppuG628uL5uT8hfx1ABy0mkUmhjboNOLcTlHNqUC lF7UnBvkQjTEDv88S2nBt1wgwwRDl9aypMJy//79Pr7EBH X-Google-Smtp-Source: AGHT+IGnQgMQ6ljR2JBrzMKmrdpD7zsaV/+e5VHw/izKEHqaMIH+GBFGZ3WcP7e+8tOrq6CB4YTdEQ== X-Received: by 2002:a17:902:ccce:b0:1f3:2e31:f83a with SMTP id d9443c01a7336-1fa23f1d31fmr80113845ad.46.1719316016716; Tue, 25 Jun 2024 04:46:56 -0700 (PDT) From: frank.chang@sifive.com To: qemu-devel@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , qemu-riscv@nongnu.org (open list:RISC-V TCG CPUs), Frank Chang , Jerry Zhang Jian , Max Chou Subject: [PATCH v3 3/6] target/riscv: Add MISA extension implied rules Date: Tue, 25 Jun 2024 19:46:26 +0800 Message-ID: <20240625114629.27793-4-frank.chang@sifive.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240625114629.27793-1-frank.chang@sifive.com> References: <20240625114629.27793-1-frank.chang@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=frank.chang@sifive.com; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1719316088836100003 Content-Type: text/plain; charset="utf-8" From: Frank Chang Add MISA extension implied rules to enable the implied extensions of MISA recursively. Signed-off-by: Frank Chang Reviewed-by: Jerry Zhang Jian Tested-by: Max Chou Reviewed-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 50 +++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 49 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 7b071ade04..b463bd8370 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -2250,8 +2250,56 @@ RISCVCPUProfile *riscv_profiles[] =3D { NULL, }; =20 +static RISCVCPUImpliedExtsRule RVA_IMPLIED =3D { + .is_misa =3D true, + .ext =3D RVA, + .implied_multi_exts =3D { + CPU_CFG_OFFSET(ext_zalrsc), CPU_CFG_OFFSET(ext_zaamo), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + +static RISCVCPUImpliedExtsRule RVD_IMPLIED =3D { + .is_misa =3D true, + .ext =3D RVD, + .implied_misa_exts =3D RVF, + .implied_multi_exts =3D { RISCV_IMPLIED_EXTS_RULE_END }, +}; + +static RISCVCPUImpliedExtsRule RVF_IMPLIED =3D { + .is_misa =3D true, + .ext =3D RVF, + .implied_multi_exts =3D { + CPU_CFG_OFFSET(ext_zicsr), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + +static RISCVCPUImpliedExtsRule RVM_IMPLIED =3D { + .is_misa =3D true, + .ext =3D RVM, + .implied_multi_exts =3D { + CPU_CFG_OFFSET(ext_zmmul), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + +static RISCVCPUImpliedExtsRule RVV_IMPLIED =3D { + .is_misa =3D true, + .ext =3D RVV, + .implied_multi_exts =3D { + CPU_CFG_OFFSET(ext_zve64d), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + RISCVCPUImpliedExtsRule *riscv_misa_ext_implied_rules[] =3D { - NULL + &RVA_IMPLIED, &RVD_IMPLIED, &RVF_IMPLIED, + &RVM_IMPLIED, &RVV_IMPLIED, NULL }; =20 RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[] =3D { --=20 2.43.2