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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:660:330f:2::dd; envelope-from=ines.varhol@telecom-paris.fr; helo=zproxy2.enst.fr X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @telecom-paris.fr) X-ZM-MESSAGEID: 1719049565397100014 Content-Type: text/plain; charset="utf-8" This commit creates a clock in STM32L4x5 SYSCFG and wires it up to the corresponding clock from STM32L4x5 RCC. Signed-off-by: In=C3=A8s Varhol Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Luc Michel --- include/hw/misc/stm32l4x5_syscfg.h | 1 + hw/arm/stm32l4x5_soc.c | 2 ++ hw/misc/stm32l4x5_syscfg.c | 19 +++++++++++++++++-- 3 files changed, 20 insertions(+), 2 deletions(-) diff --git a/include/hw/misc/stm32l4x5_syscfg.h b/include/hw/misc/stm32l4x5= _syscfg.h index 23bb564150..c450df2b9e 100644 --- a/include/hw/misc/stm32l4x5_syscfg.h +++ b/include/hw/misc/stm32l4x5_syscfg.h @@ -48,6 +48,7 @@ struct Stm32l4x5SyscfgState { uint32_t swpr2; =20 qemu_irq gpio_out[GPIO_NUM_PINS]; + Clock *clk; }; =20 #endif diff --git a/hw/arm/stm32l4x5_soc.c b/hw/arm/stm32l4x5_soc.c index 38f7a2d5d9..fb2afa6cfe 100644 --- a/hw/arm/stm32l4x5_soc.c +++ b/hw/arm/stm32l4x5_soc.c @@ -236,6 +236,8 @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc,= Error **errp) =20 /* System configuration controller */ busdev =3D SYS_BUS_DEVICE(&s->syscfg); + qdev_connect_clock_in(DEVICE(&s->syscfg), "clk", + qdev_get_clock_out(DEVICE(&(s->rcc)), "syscfg-out")); if (!sysbus_realize(busdev, errp)) { return; } diff --git a/hw/misc/stm32l4x5_syscfg.c b/hw/misc/stm32l4x5_syscfg.c index a5a1ce2680..a947a9e036 100644 --- a/hw/misc/stm32l4x5_syscfg.c +++ b/hw/misc/stm32l4x5_syscfg.c @@ -26,6 +26,9 @@ #include "trace.h" #include "hw/irq.h" #include "migration/vmstate.h" +#include "hw/clock.h" +#include "hw/qdev-clock.h" +#include "qapi/error.h" #include "hw/misc/stm32l4x5_syscfg.h" #include "hw/gpio/stm32l4x5_gpio.h" =20 @@ -225,12 +228,22 @@ static void stm32l4x5_syscfg_init(Object *obj) qdev_init_gpio_in(DEVICE(obj), stm32l4x5_syscfg_set_irq, GPIO_NUM_PINS * NUM_GPIOS); qdev_init_gpio_out(DEVICE(obj), s->gpio_out, GPIO_NUM_PINS); + s->clk =3D qdev_init_clock_in(DEVICE(s), "clk", NULL, s, 0); +} + +static void stm32l4x5_syscfg_realize(DeviceState *dev, Error **errp) +{ + Stm32l4x5SyscfgState *s =3D STM32L4X5_SYSCFG(dev); + if (!clock_has_source(s->clk)) { + error_setg(errp, "SYSCFG: clk input must be connected"); + return; + } } =20 static const VMStateDescription vmstate_stm32l4x5_syscfg =3D { .name =3D TYPE_STM32L4X5_SYSCFG, - .version_id =3D 1, - .minimum_version_id =3D 1, + .version_id =3D 2, + .minimum_version_id =3D 2, .fields =3D (VMStateField[]) { VMSTATE_UINT32(memrmp, Stm32l4x5SyscfgState), VMSTATE_UINT32(cfgr1, Stm32l4x5SyscfgState), @@ -241,6 +254,7 @@ static const VMStateDescription vmstate_stm32l4x5_syscf= g =3D { VMSTATE_UINT32(swpr, Stm32l4x5SyscfgState), VMSTATE_UINT32(skr, Stm32l4x5SyscfgState), VMSTATE_UINT32(swpr2, Stm32l4x5SyscfgState), + VMSTATE_CLOCK(clk, Stm32l4x5SyscfgState), VMSTATE_END_OF_LIST() } }; @@ -251,6 +265,7 @@ static void stm32l4x5_syscfg_class_init(ObjectClass *kl= ass, void *data) ResettableClass *rc =3D RESETTABLE_CLASS(klass); =20 dc->vmsd =3D &vmstate_stm32l4x5_syscfg; + dc->realize =3D stm32l4x5_syscfg_realize; rc->phases.hold =3D stm32l4x5_syscfg_hold_reset; } =20 --=20 2.43.2 From nobody Mon Nov 25 00:50:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=telecom-paris.fr ARC-Seal: i=1; a=rsa-sha256; t=1719049564; cv=none; d=zohomail.com; s=zohoarc; b=K0ZkkCuRdwmXH5wdp/buTUvAizi+gGcmtNlVPa6vUqZICkcAnJm8MkARYtgnYH3SmObVf9AK4HSkIBwheJtP6RFAlaCg/DH69YgixizFJCRdYhg64Ozdlo6RhRYm+fh+G2GTOSYDbpJc5O23W6zwtibCWHeUGjtOufE2+MUt2Z8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1719049564; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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t=1719049472; bh=ujbcGKP8+6XadKvbLhzG5RyhLX8RH5RysSuKMS0bOp4=; h=From:To:Date:Message-ID:MIME-Version; b=tx8gNkpHL4MzRHNy9SjTiGpenXm5mmW7b8ONoPGRpbX0O1qxmQ3L/1MfMoKexlc+N 8RnZcjhqxg0wyomRamNL+71B7uvyonfO8L834zlh1makiWLt9Qes0rHrRt55sdwetB ACVYqWk8oGNGjPi7RfAes7qlTrSOqdH7/LX2htfQ= X-Virus-Scanned: amavis at enst.fr From: =?UTF-8?q?In=C3=A8s=20Varhol?= To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Peter Maydell , Laurent Vivier , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Luc Michel , =?UTF-8?q?In=C3=A8s=20Varhol?= , Arnaud Minier , qemu-arm@nongnu.org, Thomas Huth , Damien Hedde Subject: [PATCH v4 2/3] hw/clock: Expose 'qtest-clock-period' QOM property for QTests Date: Sat, 22 Jun 2024 11:43:54 +0200 Message-ID: <20240622094402.244604-3-ines.varhol@telecom-paris.fr> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240622094402.244604-1-ines.varhol@telecom-paris.fr> References: <20240622094402.244604-1-ines.varhol@telecom-paris.fr> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=137.194.2.221; envelope-from=ines.varhol@telecom-paris.fr; helo=zproxy2.enst.fr X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @telecom-paris.fr) X-ZM-MESSAGEID: 1719049565239100008 Content-Type: text/plain; charset="utf-8" Expose the clock period via the QOM 'qtest-clock-period' property so it can be used in QTests. This property is only accessible in QTests (not via HMP). Signed-off-by: In=C3=A8s Varhol Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Luc Michel --- docs/devel/clocks.rst | 6 ++++++ hw/core/clock.c | 16 ++++++++++++++++ 2 files changed, 22 insertions(+) diff --git a/docs/devel/clocks.rst b/docs/devel/clocks.rst index 177ee1c90d..3f744f2be1 100644 --- a/docs/devel/clocks.rst +++ b/docs/devel/clocks.rst @@ -358,6 +358,12 @@ humans (for instance in debugging), use ``clock_displa= y_freq()``, which returns a prettified string-representation, e.g. "33.3 MHz". The caller must free the string with g_free() after use. =20 +It's also possible to retrieve the clock period from a QTest by +accessing QOM property ``qtest-clock-period`` using a QMP command. +This property is only present when the device is being run under +the ``qtest`` accelerator; it is not available when QEMU is +being run normally. + Calculating expiry deadlines ---------------------------- =20 diff --git a/hw/core/clock.c b/hw/core/clock.c index e212865307..cbe7b1bc46 100644 --- a/hw/core/clock.c +++ b/hw/core/clock.c @@ -13,6 +13,8 @@ =20 #include "qemu/osdep.h" #include "qemu/cutils.h" +#include "qapi/visitor.h" +#include "sysemu/qtest.h" #include "hw/clock.h" #include "trace.h" =20 @@ -158,6 +160,15 @@ bool clock_set_mul_div(Clock *clk, uint32_t multiplier= , uint32_t divider) return true; } =20 +static void clock_period_prop_get(Object *obj, Visitor *v, const char *nam= e, + void *opaque, Error **errp) +{ + Clock *clk =3D CLOCK(obj); + uint64_t period =3D clock_get(clk); + visit_type_uint64(v, name, &period, errp); +} + + static void clock_initfn(Object *obj) { Clock *clk =3D CLOCK(obj); @@ -166,6 +177,11 @@ static void clock_initfn(Object *obj) clk->divider =3D 1; =20 QLIST_INIT(&clk->children); + + if (qtest_enabled()) { + object_property_add(obj, "qtest-clock-period", "uint64", + clock_period_prop_get, NULL, NULL, NULL); + } } =20 static void clock_finalizefn(Object *obj) --=20 2.43.2 From nobody Mon Nov 25 00:50:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=telecom-paris.fr ARC-Seal: i=1; a=rsa-sha256; t=1719049564; cv=none; d=zohomail.com; s=zohoarc; b=gzJztWVwZc9Ak4DZQCv7KQhxBckVP7zN5mot7eCfhn4rRcFeBd5ebqNvUjabgsMzmv6y4U4USBtTBGnJoqd8Ct/rmjzfO5M+Ps54PsEBy53YusNqNvHbnDJ/lvnocMBmrmnlYAthe6aLnDDrUh0LDqeIhosh/NqSSK51w3Q+IEc= ARC-Message-Signature: i=1; a=rsa-sha256; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=137.194.2.221; envelope-from=ines.varhol@telecom-paris.fr; helo=zproxy2.enst.fr X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @telecom-paris.fr) X-ZM-MESSAGEID: 1719049565384100013 Content-Type: text/plain; charset="utf-8" For USART, GPIO and SYSCFG devices, check that clock frequency before and after enabling the peripheral clock in RCC is correct. Signed-off-by: In=C3=A8s Varhol Reviewed-by: Peter Maydell Reviewed-by: Luc Michel --- tests/qtest/stm32l4x5.h | 42 +++++++++++++++++++++++++++++ tests/qtest/stm32l4x5_gpio-test.c | 23 ++++++++++++++++ tests/qtest/stm32l4x5_syscfg-test.c | 20 ++++++++++++-- tests/qtest/stm32l4x5_usart-test.c | 26 ++++++++++++++++++ 4 files changed, 109 insertions(+), 2 deletions(-) create mode 100644 tests/qtest/stm32l4x5.h diff --git a/tests/qtest/stm32l4x5.h b/tests/qtest/stm32l4x5.h new file mode 100644 index 0000000000..2d21cc666c --- /dev/null +++ b/tests/qtest/stm32l4x5.h @@ -0,0 +1,42 @@ +/* + * QTest testcase header for STM32L4X5 : + * used for consolidating common objects in stm32l4x5_*-test.c + * + * Copyright (c) 2024 Arnaud Minier + * Copyright (c) 2024 In=C3=A8s Varhol + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#include "libqtest.h" + +/* copied from clock.h */ +#define CLOCK_PERIOD_1SEC (1000000000llu << 32) +#define CLOCK_PERIOD_FROM_HZ(hz) (((hz) !=3D 0) ? CLOCK_PERIOD_1SEC / (hz)= : 0u) +/* + * MSI (4 MHz) is used as system clock source after startup + * from Reset. + * AHB, APB1 and APB2 prescalers are set to 1 at reset. + */ +#define SYSCLK_PERIOD CLOCK_PERIOD_FROM_HZ(4000000) +#define RCC_AHB2ENR 0x4002104C +#define RCC_APB1ENR1 0x40021058 +#define RCC_APB1ENR2 0x4002105C +#define RCC_APB2ENR 0x40021060 + + +static inline uint64_t get_clock_period(QTestState *qts, const char *path) +{ + uint64_t clock_period =3D 0; + QDict *r; + + r =3D qtest_qmp(qts, "{ 'execute': 'qom-get', 'arguments':" + " { 'path': %s, 'property': 'qtest-clock-period'} }", path); + g_assert_false(qdict_haskey(r, "error")); + clock_period =3D qdict_get_int(r, "return"); + qobject_unref(r); + return clock_period; +} + + diff --git a/tests/qtest/stm32l4x5_gpio-test.c b/tests/qtest/stm32l4x5_gpio= -test.c index 72a7823406..c0686c7b30 100644 --- a/tests/qtest/stm32l4x5_gpio-test.c +++ b/tests/qtest/stm32l4x5_gpio-test.c @@ -10,6 +10,7 @@ =20 #include "qemu/osdep.h" #include "libqtest-single.h" +#include "stm32l4x5.h" =20 #define GPIO_BASE_ADDR 0x48000000 #define GPIO_SIZE 0x400 @@ -505,6 +506,26 @@ static void test_bsrr_brr(const void *data) gpio_writel(gpio, ODR, reset(gpio, ODR)); } =20 +static void test_clock_enable(void) +{ + /* + * For each GPIO, enable its clock in RCC + * and check that its clock period changes to SYSCLK_PERIOD + */ + unsigned int gpio_id; + + for (uint32_t gpio =3D GPIO_A; gpio <=3D GPIO_H; gpio +=3D GPIO_B - GP= IO_A) { + gpio_id =3D get_gpio_id(gpio); + g_autofree char *path =3D g_strdup_printf("/machine/soc/gpio%c/clk= ", + gpio_id + 'a'); + g_assert_cmpuint(get_clock_period(global_qtest, path), =3D=3D, 0); + /* Enable the gpio clock */ + writel(RCC_AHB2ENR, readl(RCC_AHB2ENR) | (0x1 << gpio_id)); + g_assert_cmpuint(get_clock_period(global_qtest, path), =3D=3D, + SYSCLK_PERIOD); + } +} + int main(int argc, char **argv) { int ret; @@ -556,6 +577,8 @@ int main(int argc, char **argv) qtest_add_data_func("stm32l4x5/gpio/test_bsrr_brr2", test_data(GPIO_D, 0), test_bsrr_brr); + qtest_add_func("stm32l4x5/gpio/test_clock_enable", + test_clock_enable); =20 qtest_start("-machine b-l475e-iot01a"); ret =3D g_test_run(); diff --git a/tests/qtest/stm32l4x5_syscfg-test.c b/tests/qtest/stm32l4x5_sy= scfg-test.c index 506ca08bc2..8eaffe43ea 100644 --- a/tests/qtest/stm32l4x5_syscfg-test.c +++ b/tests/qtest/stm32l4x5_syscfg-test.c @@ -10,6 +10,7 @@ =20 #include "qemu/osdep.h" #include "libqtest-single.h" +#include "stm32l4x5.h" =20 #define SYSCFG_BASE_ADDR 0x40010000 #define SYSCFG_MEMRMP 0x00 @@ -26,7 +27,9 @@ #define INVALID_ADDR 0x2C =20 /* SoC forwards GPIOs to SysCfg */ -#define SYSCFG "/machine/soc" +#define SOC "/machine/soc" +#define SYSCFG "/machine/soc/syscfg" +#define SYSCFG_CLK "/machine/soc/syscfg/clk" #define EXTI "/machine/soc/exti" =20 static void syscfg_writel(unsigned int offset, uint32_t value) @@ -41,7 +44,7 @@ static uint32_t syscfg_readl(unsigned int offset) =20 static void syscfg_set_irq(int num, int level) { - qtest_set_irq_in(global_qtest, SYSCFG, NULL, num, level); + qtest_set_irq_in(global_qtest, SOC, NULL, num, level); } =20 static void system_reset(void) @@ -301,6 +304,17 @@ static void test_irq_gpio_multiplexer(void) syscfg_writel(SYSCFG_EXTICR1, 0x00000000); } =20 +static void test_clock_enable(void) +{ + g_assert_cmpuint(get_clock_period(global_qtest, SYSCFG_CLK), =3D=3D, 0= ); + + /* Enable SYSCFG clock */ + writel(RCC_APB2ENR, readl(RCC_APB2ENR) | (0x1 << 0)); + + g_assert_cmpuint(get_clock_period(global_qtest, SYSCFG_CLK), =3D=3D, + SYSCLK_PERIOD); +} + int main(int argc, char **argv) { int ret; @@ -325,6 +339,8 @@ int main(int argc, char **argv) test_irq_pin_multiplexer); qtest_add_func("stm32l4x5/syscfg/test_irq_gpio_multiplexer", test_irq_gpio_multiplexer); + qtest_add_func("stm32l4x5/syscfg/test_clock_enable", + test_clock_enable); =20 qtest_start("-machine b-l475e-iot01a"); ret =3D g_test_run(); diff --git a/tests/qtest/stm32l4x5_usart-test.c b/tests/qtest/stm32l4x5_usa= rt-test.c index 8902518233..4bad3603e8 100644 --- a/tests/qtest/stm32l4x5_usart-test.c +++ b/tests/qtest/stm32l4x5_usart-test.c @@ -12,6 +12,7 @@ #include "libqtest.h" #include "hw/misc/stm32l4x5_rcc_internals.h" #include "hw/registerfields.h" +#include "stm32l4x5.h" =20 #define RCC_BASE_ADDR 0x40021000 /* Use USART 1 ADDR, assume the others work the same */ @@ -296,6 +297,30 @@ static void test_send_str(void) qtest_quit(qts); } =20 +static void check_clock(QTestState *qts, const char *path, uint32_t rcc_re= g, + uint32_t reg_offset) +{ + g_assert_cmpuint(get_clock_period(qts, path), =3D=3D, 0); + qtest_writel(qts, rcc_reg, qtest_readl(qts, rcc_reg) | (0x1 << reg_off= set)); + g_assert_cmpuint(get_clock_period(qts, path), =3D=3D, SYSCLK_PERIOD); +} + +static void test_clock_enable(void) +{ + /* + * For each USART device, enable its clock in RCC + * and check that its clock frequency is SYSCLK_PERIOD + */ + QTestState *qts =3D qtest_init("-M b-l475e-iot01a"); + + check_clock(qts, "machine/soc/usart[0]/clk", RCC_APB2ENR, 14); + check_clock(qts, "machine/soc/usart[1]/clk", RCC_APB1ENR1, 17); + check_clock(qts, "machine/soc/usart[2]/clk", RCC_APB1ENR1, 18); + check_clock(qts, "machine/soc/uart[0]/clk", RCC_APB1ENR1, 19); + check_clock(qts, "machine/soc/uart[1]/clk", RCC_APB1ENR1, 20); + check_clock(qts, "machine/soc/lpuart1/clk", RCC_APB1ENR2, 0); +} + int main(int argc, char **argv) { int ret; @@ -308,6 +333,7 @@ int main(int argc, char **argv) qtest_add_func("stm32l4x5/usart/send_char", test_send_char); qtest_add_func("stm32l4x5/usart/receive_str", test_receive_str); qtest_add_func("stm32l4x5/usart/send_str", test_send_str); + qtest_add_func("stm32l4x5/usart/clock_enable", test_clock_enable); ret =3D g_test_run(); =20 return ret; --=20 2.43.2