From nobody Mon Nov 25 02:09:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1718980834; cv=none; d=zohomail.com; s=zohoarc; b=k0EmNwqJ+dI/pFW6tZo/2VqPKFNfDq2xOsiJ1Ne7QeRoFTRaa8t7UjhLeaYLklD1YQl2I/M4aAKPqxlSLb1uM07GVE+IRjt4Ld9Ptrm9A40kPJx80lTgHGQ+dSlE4yZZAp/vDpEhjYqN+PoCggF8HthHVqPMTa0RpSUAhlDP8sA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1718980834; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=pbW4VmHlRcXOaBBuGCKxn/sE/2fViPqLSFr+O68nhEo=; b=PbHihTEpLmc0qnq4ujzvXRu/CHXKelNOErl55LjkSQBGJlgzVjeh+JkSMYVw2TGjv21bdPVTgdVOTI3rL3N5aRbIbh2/3mLPTOJJBqxRS7NybMeet6c6vVos08aLj93QLLxowUSyZ0uL/swi/vm2IDiu1QdQdjRR3F+Ag8f+Zh4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1718980834932424.6146940644851; Fri, 21 Jun 2024 07:40:34 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sKfQV-0006pm-Ht; Fri, 21 Jun 2024 10:39:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sKfQT-0006pD-8v for qemu-devel@nongnu.org; Fri, 21 Jun 2024 10:39:41 -0400 Received: from mail-pf1-x42d.google.com ([2607:f8b0:4864:20::42d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sKfQR-0007xu-Eb for qemu-devel@nongnu.org; Fri, 21 Jun 2024 10:39:40 -0400 Received: by mail-pf1-x42d.google.com with SMTP id d2e1a72fcca58-7041053c0fdso1510558b3a.3 for ; Fri, 21 Jun 2024 07:39:39 -0700 (PDT) Received: from amd.. ([2804:7f0:b401:1654:3e7c:3fff:fe7a:e83b]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7065130e8e2sm1466513b3a.215.2024.06.21.07.39.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Jun 2024 07:39:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1718980778; x=1719585578; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=pbW4VmHlRcXOaBBuGCKxn/sE/2fViPqLSFr+O68nhEo=; b=WxNOYfvvAXintAio7+uvQcUpcQQpzCP+z7OnQrjbpwohxsCZOlf2JE4yuD9g+PtXCV AyhqDB73M1bcOaAYbpjSbL8Ht9AhoCxZ3lbbxj66qFDyBQYj1jb4OOTr7Shhuy51JjqQ KL/pn4hvyGk4RYE/yKZmdADcp4rN2nervkBLmSs4A4CJObw+2N08lagBIil/TRmScJQs HZ9hc26E/CDZdf+cC4lILxVeTTYi3IyR7516hSB6FQME8EvmsSClHKYWpHigY09k6Axc H6kJkXyfl8f12xLUmvS7bhLjPeh1TIJ7ZJHBmdqVvo3O4Iclv5V1Ii7xoA6xW2KBBDh6 p+yA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1718980778; x=1719585578; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pbW4VmHlRcXOaBBuGCKxn/sE/2fViPqLSFr+O68nhEo=; b=OXwogNAXZinoTe1LzfqnuhBMFi2m143nI0QcHa6wpNa2rGflMt9oKGR0+cFWXaMAkw RJKQ2sPB/YyOUyyELZeHJrzPVgJrUzsKEIq8Bkm8tRTok+or2PvUs2k7c+GPDrLaaVKJ ad5/+9zkLEB7fjWvHXgr/FFkROL/JIUMOE0hh95QCYZRzbwljbsgJbLSxiERXDd19/Zk TvXyGXztxKuLql9cEhI7coAkRgtjsrnwAox1la/zRATyIsVPMhcst1Du5XqfLAYZZodd 4z5rZmzhc1C6iji7QmwdNUsj1QcypOPmdzy6hLY/282kb6hf8buvCNYRIdXDVCCc51uG KnZQ== X-Gm-Message-State: AOJu0YwbggK/AG1ldj965OglExGX8lmktYUJxoEPbIgirRbZOM/dUadD Y5mY4glxWKVA4Q7yn17nDLF2vI+V7PPHc5xAJ+GzIbG3I/R7XKxC/c7xWSMSs/Hw+JnF6ayyxlb pp/A= X-Google-Smtp-Source: AGHT+IGDzPLTZJ+ZyBvyT59inRM7G/nSyZkGJRS7o5jFWQYArBuKTJLtJ9TMVYI+S8oUHqoTcidnYQ== X-Received: by 2002:a05:6a20:891f:b0:1b4:1560:f80f with SMTP id adf61e73a8af0-1bcbb697107mr8106408637.56.1718980777558; Fri, 21 Jun 2024 07:39:37 -0700 (PDT) From: Gustavo Romero To: qemu-devel@nongnu.org, alex.bennee@linaro.org, richard.henderson@linaro.org Cc: philmd@linaro.org, peter.maydell@linaro.org, gustavo.romero@linaro.org Subject: [PATCH v2 1/2] target/arm: Move initialization of debug ID registers Date: Fri, 21 Jun 2024 14:39:02 +0000 Message-Id: <20240621143903.3598230-2-gustavo.romero@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240621143903.3598230-1-gustavo.romero@linaro.org> References: <20240621143903.3598230-1-gustavo.romero@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=gustavo.romero@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1718980835928100001 Content-Type: text/plain; charset="utf-8" Move the initialization of the debug ID registers to aa32_max_features, which is used to set the 32-bit ID registers. This ensures that the debug ID registers are consistently set for the max CPU in a single place. Signed-off-by: Gustavo Romero Reviewed-by: Richard Henderson --- target/arm/cpu.h | 2 ++ target/arm/tcg/cpu32.c | 30 +++++++++++++++++++++++++++--- target/arm/tcg/cpu64.c | 2 +- 3 files changed, 30 insertions(+), 4 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 3841359d0f..d8eb986a04 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2299,6 +2299,8 @@ FIELD(DBGDEVID, DOUBLELOCK, 20, 4) FIELD(DBGDEVID, AUXREGS, 24, 4) FIELD(DBGDEVID, CIDMASK, 28, 4) =20 +FIELD(DBGDEVID1, PCSROFFSET, 0, 4) + FIELD(MVFR0, SIMDREG, 0, 4) FIELD(MVFR0, FPSP, 4, 4) FIELD(MVFR0, FPDP, 8, 4) diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c index bdd82d912a..b155a0136f 100644 --- a/target/arm/tcg/cpu32.c +++ b/target/arm/tcg/cpu32.c @@ -87,6 +87,33 @@ void aa32_max_features(ARMCPU *cpu) t =3D FIELD_DP32(t, ID_DFR0, PERFMON, 6); /* FEAT_PMUv3p5 */ cpu->isar.id_dfr0 =3D t; =20 + /* Debug ID registers. */ + + /* Bit[15] is RES1, Bit[13] and Bits[11:0] are RES0. */ + t =3D 0x00008000; + t =3D FIELD_DP32(t, DBGDIDR, SE_IMP, 1); + t =3D FIELD_DP32(t, DBGDIDR, NSUHD_IMP, 1); + t =3D FIELD_DP32(t, DBGDIDR, VERSION, 6); /* Armv8 debug */ + t =3D FIELD_DP32(t, DBGDIDR, CTX_CMPS, 1); + t =3D FIELD_DP32(t, DBGDIDR, BRPS, 5); + t =3D FIELD_DP32(t, DBGDIDR, WRPS, 3); + cpu->isar.dbgdidr =3D t; + + t =3D FIELD_DP32(t, DBGDEVID, PCSAMPLE, 3); + t =3D FIELD_DP32(t, DBGDEVID, WPADDRMASK, 1); + t =3D FIELD_DP32(t, DBGDEVID, BPADDRMASK, 15); + t =3D FIELD_DP32(t, DBGDEVID, VECTORCATCH, 0); + t =3D FIELD_DP32(t, DBGDEVID, VIRTEXTNS, 1); + t =3D FIELD_DP32(t, DBGDEVID, DOUBLELOCK, 1); + t =3D FIELD_DP32(t, DBGDEVID, AUXREGS, 0); + t =3D FIELD_DP32(t, DBGDEVID, CIDMASK, 0); + cpu->isar.dbgdevid =3D t; + + /* Bits[31:4] are RES0. */ + t =3D 0; + t =3D FIELD_DP32(t, DBGDEVID1, PCSROFFSET, 2); + cpu->isar.dbgdevid1 =3D t; + t =3D cpu->isar.id_dfr1; t =3D FIELD_DP32(t, ID_DFR1, HPMN0, 1); /* FEAT_HPMN0 */ cpu->isar.id_dfr1 =3D t; @@ -955,9 +982,6 @@ static void arm_max_initfn(Object *obj) cpu->isar.id_isar4 =3D 0x00011142; cpu->isar.id_isar5 =3D 0x00011121; cpu->isar.id_isar6 =3D 0; - cpu->isar.dbgdidr =3D 0x3516d000; - cpu->isar.dbgdevid =3D 0x00110f13; - cpu->isar.dbgdevid1 =3D 0x2; cpu->isar.reset_pmcr_el0 =3D 0x41013000; cpu->clidr =3D 0x0a200023; cpu->ccsidr[0] =3D 0x701fe00a; /* 32KB L1 dcache */ diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 0899251eef..71e1bfcd4e 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -1167,7 +1167,7 @@ void aarch64_max_tcg_initfn(Object *obj) =20 t =3D cpu->isar.id_aa64isar2; t =3D FIELD_DP64(t, ID_AA64ISAR2, MOPS, 1); /* FEAT_MOPS */ - t =3D FIELD_DP64(t, ID_AA64ISAR2, BC, 1); /* FEAT_HBC */ + t =3D FIELD_DP64(t, ID_AA64ISAR2, BC, 1); /* FEAT_HBC */ t =3D FIELD_DP64(t, ID_AA64ISAR2, WFXT, 2); /* FEAT_WFxT */ cpu->isar.id_aa64isar2 =3D t; =20 --=20 2.34.1 From nobody Mon Nov 25 02:09:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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([2804:7f0:b401:1654:3e7c:3fff:fe7a:e83b]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7065130e8e2sm1466513b3a.215.2024.06.21.07.39.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Jun 2024 07:39:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1718980780; x=1719585580; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+1bsxXTyJYNTiYjX7+F9Hoal/1vE9r9yDkUQkjviuNk=; b=SD08RSKwB0AQc4UbyLAwuSvM/Gh4p7iO+ZDm9E04lT62HkgMzQDh7M49oO/fTV9R0a m2JD9xQF6iwbYSdrRimRngJ9kpncSAGlaAb5qRnKFkJLjU79Xs+eeCuG+LFjRMhx0TyX VrE1G58HuynNxbhqhmzS7oU8wnFhpT7juLyXTliSqxgaOq9yeKdYw+ZcgnM4nxq2SGsA BZ6zvzd6/OUOnWUx4kdSGjHFBBLWpxy3A5XuOadhD8UoDZWQfsPDkxL/9DA+BOb4tQ26 8G7PxY/aGnT8UTwC15az8FQPxrRjfbq69DixB17Or8kVgl/jHXRrzEqdAfBlBVFc5aCQ sbLQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1718980780; x=1719585580; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+1bsxXTyJYNTiYjX7+F9Hoal/1vE9r9yDkUQkjviuNk=; b=RxL4eC9p0ZJ3OQz5bD/+B6agCXxWgg0dCDLgRU+i44zNNfwfD4pjsMq9V6He87SHqK q8g2ffEV/J6UloHwnmsuLnOfWL7k71SXmK7y88xxwRTHg8A3W3eaqZvcybZRs/mAHDiL wr4tklDm0PqpwHpQWFNpnPGYsc+RxLxC7D6GrSaBN4K9GUS8f0S+QSv0fA94AIzi+wWA 7KmndmJDbu/UcMHQ9eJKtLHCRA7zKQmJs2s8w3zxrc0Vm4INpa2NV5/aNfgwr5WdxWHW ZWbGihYU27kcS17bmq2WzLbmp3D/fiHsK/wg8wfSiK5lSLTH3ioCjzsrdawvGBiKAT2N 3QhQ== X-Gm-Message-State: AOJu0Yzf8g2YAjVKdcBul8Tgm3pwz1fof36zT0LRixQo5UDgx/uXEHjs NlCrk3FAJTj6piUAUFk31ydhGRIPZGDm56ysHI4UdPxCZJTHmKic76twdQArv1XKoMvHzwlwqqV W7qI= X-Google-Smtp-Source: AGHT+IH8BLxLJ54xeKY1YClhznEvR5IvrJ2TLCmTEZE+sUd/SfoBumF+gup9ZGdUgxUXz76aB6aTlw== X-Received: by 2002:aa7:9294:0:b0:706:616d:2215 with SMTP id d2e1a72fcca58-706616d235bmr476590b3a.21.1718980779902; Fri, 21 Jun 2024 07:39:39 -0700 (PDT) From: Gustavo Romero To: qemu-devel@nongnu.org, alex.bennee@linaro.org, richard.henderson@linaro.org Cc: philmd@linaro.org, peter.maydell@linaro.org, gustavo.romero@linaro.org Subject: [PATCH v2 2/2] target/arm: Enable FEAT_Debugv8p8 for -cpu max Date: Fri, 21 Jun 2024 14:39:03 +0000 Message-Id: <20240621143903.3598230-3-gustavo.romero@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240621143903.3598230-1-gustavo.romero@linaro.org> References: <20240621143903.3598230-1-gustavo.romero@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=gustavo.romero@linaro.org; helo=mail-pf1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1718980807846100001 Content-Type: text/plain; charset="utf-8" Enable FEAT_Debugv8p8 for max CPU. This feature is out of scope for QEMU since it concerns the external debug interface for JTAG, but is mandatory in Armv8.8 implementations, hence it is reported as supported in the ID registers. Signed-off-by: Gustavo Romero Reviewed-by: Richard Henderson --- target/arm/tcg/cpu32.c | 6 +++--- target/arm/tcg/cpu64.c | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c index b155a0136f..a1273a73a3 100644 --- a/target/arm/tcg/cpu32.c +++ b/target/arm/tcg/cpu32.c @@ -82,8 +82,8 @@ void aa32_max_features(ARMCPU *cpu) cpu->isar.id_pfr2 =3D t; =20 t =3D cpu->isar.id_dfr0; - t =3D FIELD_DP32(t, ID_DFR0, COPDBG, 9); /* FEAT_Debugv8p4 */ - t =3D FIELD_DP32(t, ID_DFR0, COPSDBG, 9); /* FEAT_Debugv8p4 */ + t =3D FIELD_DP32(t, ID_DFR0, COPDBG, 10); /* FEAT_Debugv8p8 */ + t =3D FIELD_DP32(t, ID_DFR0, COPSDBG, 10); /* FEAT_Debugv8p8 */ t =3D FIELD_DP32(t, ID_DFR0, PERFMON, 6); /* FEAT_PMUv3p5 */ cpu->isar.id_dfr0 =3D t; =20 @@ -93,7 +93,7 @@ void aa32_max_features(ARMCPU *cpu) t =3D 0x00008000; t =3D FIELD_DP32(t, DBGDIDR, SE_IMP, 1); t =3D FIELD_DP32(t, DBGDIDR, NSUHD_IMP, 1); - t =3D FIELD_DP32(t, DBGDIDR, VERSION, 6); /* Armv8 debug */ + t =3D FIELD_DP32(t, DBGDIDR, VERSION, 10); /* FEAT_Debugv8p8 */ t =3D FIELD_DP32(t, DBGDIDR, CTX_CMPS, 1); t =3D FIELD_DP32(t, DBGDIDR, BRPS, 5); t =3D FIELD_DP32(t, DBGDIDR, WRPS, 3); diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 71e1bfcd4e..fe232eb306 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -1253,7 +1253,7 @@ void aarch64_max_tcg_initfn(Object *obj) cpu->isar.id_aa64zfr0 =3D t; =20 t =3D cpu->isar.id_aa64dfr0; - t =3D FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 9); /* FEAT_Debugv8p4 */ + t =3D FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 10); /* FEAT_Debugv8p8 */ t =3D FIELD_DP64(t, ID_AA64DFR0, PMUVER, 6); /* FEAT_PMUv3p5 */ t =3D FIELD_DP64(t, ID_AA64DFR0, HPMN0, 1); /* FEAT_HPMN0 */ cpu->isar.id_aa64dfr0 =3D t; --=20 2.34.1