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Iglesias'" , Peter Maydell , , , "Edgar E . Iglesias" Subject: [PATCH v4 1/3] hw/misc/zynq_slcr: Add boot-mode property Date: Fri, 21 Jun 2024 18:29:04 +0530 Message-ID: <20240621125906.1300995-2-sai.pavan.boddu@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240621125906.1300995-1-sai.pavan.boddu@amd.com> References: <20240621125906.1300995-1-sai.pavan.boddu@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: None (SATLEXMB05.amd.com: sai.pavan.boddu@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000A349:EE_|PH8PR12MB7206:EE_ X-MS-Office365-Filtering-Correlation-Id: c052f004-7ccc-46b5-ebad-08dc91f1f7bb X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230037|82310400023|36860700010|1800799021|376011; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?3G9CSf9+n7ffGXgRq6P6MQYPlC31bOvnrMecGQ1c45N1/f1ytfWXbVUiThTH?= =?us-ascii?Q?MxEaAfN0qQN7WRgMIkWOjA2YtYAHOFJrOKw3KzaAuZaWXse7rEIziN0tHBgs?= =?us-ascii?Q?Fgf/xv5SthHfquVilBnoENsHXeEtyyg93bfrRg1ef0b4V898YMH6e6RB7lrS?= =?us-ascii?Q?lIz+VO2Lwouq5CWnjtraKd67OH0VhgzVo7PQT6VXazf/UZqMEJV+2f/2wRHp?= =?us-ascii?Q?NXZW54ztaCG3Y3QQTqXkZAjUqxanhcyiO/k0L4BhhxGbTlnfA4xXBfwG9gYy?= =?us-ascii?Q?7Kwq0DKGvq9NbpAad6nSFtZIGtUpjI8k7gXBuIhLuCVd1eNrApzfThlLF5SE?= =?us-ascii?Q?AbBdzlhIDKgzwX4SZE8ND9vEMpZx1nBolhYPOYmbUZ56vH0Qw2gpdSACuJoS?= =?us-ascii?Q?mvGQYOnqWZlwMSF+fJBKtS1nh8yKfj3x7D6QCky+hvDLZNSa8LNMqS7RbOGj?= =?us-ascii?Q?LVVl6CthuvOhBVJU+G2KDnHwCXbVVN7V72nsiBIlz6SpzE25fJNe4hhGokAo?= =?us-ascii?Q?q+i38z1lbzmQCjsQImU5050vGQNYdQiJ86dAblKIRfVqAOkzEILt5LF2ViDF?= =?us-ascii?Q?PgIuOdhtWuzeEqxSWuxvGxUTTzzlPAGzPTaa89qlfPCKfjfP1CU7fG2b/qFZ?= =?us-ascii?Q?3j27OludwIMQbnYa65BWmN/1yg42vkgGKxqXDTDgkN4AaVM7Jd9Wc11N7OU9?= =?us-ascii?Q?/7ydfgcqZgmlcNPtr9p35gQJ3nS0qCaH4v73bL70AatnggSwb9jzW6qgLCrP?= =?us-ascii?Q?6I1GiCtRS7Lk4OGbATmnBxPGqdcWW/MP6Rl9NG/ndwxFT6tXsOjpX2Dyq6mF?= =?us-ascii?Q?mrf66D+TP5/TUa+RxDtAlLrULhRdJ3SKMof4dJHU+Kwvy86nvxB34kB9usBg?= =?us-ascii?Q?DfItowdcu+NnwMtC8o6s0Ihe3aSLb/PT5vLYKU6uTomfjsCTjI226tw5rubV?= =?us-ascii?Q?o1OlRwkO+0pdJ5FUAmzMa2gXY+NhZVAL+d7l3MMth1JOA5y/K40oz1Ql3Y6+?= =?us-ascii?Q?a2B7JhAqI0QaSD78aiDDa2ax1c/QP25wCbmZVY6iyi47qUDi7YpdMheiAlRx?= =?us-ascii?Q?yyExPZjqJ6yw0XxCskYI+udNT1s4rmW0BxM0bm8HQkyvPBY/MPW7QkauooBk?= =?us-ascii?Q?v1fYFQOr6yB99PARTLKhH2wYhNBX8Tf9WyzXh1FePihf6QcIR+Ksajj5MtJK?= =?us-ascii?Q?Mhr0IgzTGRzGlJviAK3yig6Axa+Jo37LXFKTyG36zi339TOjqjthN+mBiJCh?= =?us-ascii?Q?bVJmaQZHKwIfCy4g5LHsNR7s69emYlT5nVB46O7Kk6KMKJ/yimIksea6fDQh?= =?us-ascii?Q?PBL1wKQ/8/A+CBoVzfSyDS/gh93ZJiuU+HD3rvUedu83R2JI8iK2FoGELUUd?= =?us-ascii?Q?7G5b6AsbJ33XY7BOpJzrAS6NEWFOT1RoCBLIFEVGAxdjqWi/AQ=3D=3D?= X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB03.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230037)(82310400023)(36860700010)(1800799021)(376011); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Jun 2024 12:59:20.3576 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c052f004-7ccc-46b5-ebad-08dc91f1f7bb X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000A349.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB7206 Received-SPF: permerror client-ip=2a01:111:f403:2414::615; envelope-from=sai.pavan.boddu@amd.com; helo=NAM11-BN8-obe.outbound.protection.outlook.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.145, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1718974891249100001 Content-Type: text/plain; charset="utf-8" boot-mode property sets user values into BOOT_MODE register, on hardware these are derived from board switches. Signed-off-by: Sai Pavan Boddu Reviewed-by: Edgar E. Iglesias Reviewed-by: Francisco Iglesias --- hw/misc/zynq_slcr.c | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/hw/misc/zynq_slcr.c b/hw/misc/zynq_slcr.c index 3412ff099ea..ad814c3a79b 100644 --- a/hw/misc/zynq_slcr.c +++ b/hw/misc/zynq_slcr.c @@ -24,6 +24,8 @@ #include "hw/registerfields.h" #include "hw/qdev-clock.h" #include "qom/object.h" +#include "hw/qdev-properties.h" +#include "qapi/error.h" =20 #ifndef ZYNQ_SLCR_ERR_DEBUG #define ZYNQ_SLCR_ERR_DEBUG 0 @@ -121,6 +123,7 @@ REG32(RST_REASON, 0x250) =20 REG32(REBOOT_STATUS, 0x258) REG32(BOOT_MODE, 0x25c) + FIELD(BOOT_MODE, BOOT_MODE, 0, 4) =20 REG32(APU_CTRL, 0x300) REG32(WDT_CLK_SEL, 0x304) @@ -195,6 +198,7 @@ struct ZynqSLCRState { Clock *ps_clk; Clock *uart0_ref_clk; Clock *uart1_ref_clk; + uint8_t boot_mode; }; =20 /* @@ -371,7 +375,7 @@ static void zynq_slcr_reset_init(Object *obj, ResetType= type) s->regs[R_FPGA_RST_CTRL] =3D 0x01F33F0F; s->regs[R_RST_REASON] =3D 0x00000040; =20 - s->regs[R_BOOT_MODE] =3D 0x00000001; + s->regs[R_BOOT_MODE] =3D s->boot_mode & R_BOOT_MODE_BOOT_MODE_MAS= K; =20 /* 0x700 - 0x7D4 */ for (i =3D 0; i < 54; i++) { @@ -588,6 +592,15 @@ static const ClockPortInitArray zynq_slcr_clocks =3D { QDEV_CLOCK_END }; =20 +static void zynq_slcr_realize(DeviceState *dev, Error **errp) +{ + ZynqSLCRState *s =3D ZYNQ_SLCR(dev); + + if (s->boot_mode > 0xF) { + error_setg(errp, "Invalid boot mode %d specified", s->boot_mode); + } +} + static void zynq_slcr_init(Object *obj) { ZynqSLCRState *s =3D ZYNQ_SLCR(obj); @@ -610,15 +623,22 @@ static const VMStateDescription vmstate_zynq_slcr =3D= { } }; =20 +static Property zynq_slcr_props[] =3D { + DEFINE_PROP_UINT8("boot-mode", ZynqSLCRState, boot_mode, 1), + DEFINE_PROP_END_OF_LIST(), +}; + static void zynq_slcr_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); ResettableClass *rc =3D RESETTABLE_CLASS(klass); =20 dc->vmsd =3D &vmstate_zynq_slcr; + dc->realize =3D zynq_slcr_realize; rc->phases.enter =3D zynq_slcr_reset_init; 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Iglesias'" , Peter Maydell , , , "Edgar E . Iglesias" Subject: [PATCH v4 2/3] hw/arm/xilinx_zynq: Add boot-mode property Date: Fri, 21 Jun 2024 18:29:05 +0530 Message-ID: <20240621125906.1300995-3-sai.pavan.boddu@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240621125906.1300995-1-sai.pavan.boddu@amd.com> References: <20240621125906.1300995-1-sai.pavan.boddu@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF0000231B:EE_|MW4PR12MB5642:EE_ X-MS-Office365-Filtering-Correlation-Id: 184162ac-68e3-45ab-48ee-08dc91f1f912 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230037|376011|36860700010|1800799021|82310400023; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?qp+orFz4vMuETUekul6yznNpampYvMbRAVGJxYo/rq3Dqt34boMQ7RSIXkae?= =?us-ascii?Q?9ptiQnGBQ9o8oFVHy5IeP5a3IIeiICib98saH9sI0j2zlxvid5/eoe+uLnTu?= =?us-ascii?Q?0HSsrVEieZA3EokJNPVggWLKloH4Sq/l8deaMTPSUlA9Xlvuvrwoydwpm8dY?= =?us-ascii?Q?nRhi5dbuJBjxUPkzhVeE8XwtsHPJhXADzwOTez1RYVi3RywrHHwiNoO/Y8X8?= =?us-ascii?Q?ip989Ll1ZjnQpNjYTySvcDpIk3+/xrkPnDEG+5yUXQh74+R5idMXRAoxKqNw?= =?us-ascii?Q?WXDls8ZDwrI1vTMaqaN5RrFSBh56PXPN761T5Ii3T3q2r6JM5rWIOJ7/7APt?= =?us-ascii?Q?ruAlhlMktlwFVthodpgra/qBnlIJVCO+tsYjR62jHYQaqydo4LRwfwc9gLIv?= =?us-ascii?Q?C2nEQ0zM3SZ4uERnQgRndC/fowLb/7BFBCh8JKNwPdaZLdbtbV7WgFNn/nZp?= =?us-ascii?Q?8SLsaAq6v2TG3W3YPPMsU0OMZ9W4HR87BombgPW6ZnAWFmFzeWV1lAeXopyK?= =?us-ascii?Q?edijDTEMWl8WwLrwTD9LvINNo8iDyp6L2ckDXSibfA1n064Y+KopvigxtA78?= =?us-ascii?Q?SRxtG9sz2DtTDt6a4QIEaIrS4a/XSBZM+4io1issjML1TUFWXUylr00T6Yj0?= =?us-ascii?Q?ifchSdTfGXRNLhl9G0fUcf/Xdf99hi69+VgdOyseVc6I391dIBRb3QVhJOBR?= =?us-ascii?Q?e4SGPjxcyXfh9nCgqLKST8ZD4dQgeCvHAPgM3WgMoRxqfyBBmiDu+SWcoxfa?= =?us-ascii?Q?ynvWuDWvCkhhLwl2bbfr3dSjRGLBmxpsTMXfXg6HgkBwtKZRKXsediVNqjpR?= =?us-ascii?Q?A/ryqh3t/Ie9Zbto+RxMnqZeutCptkE+UgKpi58BFg/B2EpsuZ+DN64OPd9q?= =?us-ascii?Q?dk1tEQm7/joS3s75bTy5xybXuUyOzGKErRXNzW2ip92z8SKX3seVHushwOE8?= =?us-ascii?Q?F7KUUr36e1z3H6it46bSxm0Ue5Qzlxhj1UD9GaZ/Jd32vzWgY2adkTkemnSo?= =?us-ascii?Q?WzAw4L7QV+FC6+KoCG+S/cnnh2Lbh1gXiYdPLgmNDuukjGegHDHeJWfSB9pD?= =?us-ascii?Q?6faafEXCsTNK6/DE8Zm2O7loWOlSDh00dbASCjfofHG7+mx1AmOSChKYfhWb?= =?us-ascii?Q?NuC5xJmtorEMTXcIfHXLDADPE1s9gyvCgS2J8krH6cP0uKZmVkZyZFnRz4SW?= =?us-ascii?Q?ZLV9zf6Q7ZFeMWWo2LzSlmipTOTVSRVINMkqEkNlalf4XIoRu5xxvGnQrSyq?= =?us-ascii?Q?1Le7IpDq2+vagdFiN+jkjkiGUCXTNodQRmTML2F0qj4qh6Uw+JPxw4gmwRAT?= =?us-ascii?Q?8aNkokysSzrUAIJCC7syic1CcMB0OeADF/88wkKa0URbbey/R4mU9rP2hiTt?= =?us-ascii?Q?JE36i9Rmq5wV7q4SIz5yF+AVeN85RBBd9qFcIYztEExSn7J3lg=3D=3D?= X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230037)(376011)(36860700010)(1800799021)(82310400023); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Jun 2024 12:59:23.0232 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 184162ac-68e3-45ab-48ee-08dc91f1f912 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF0000231B.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB5642 Received-SPF: permerror client-ip=2a01:111:f403:2009::61f; envelope-from=sai.pavan.boddu@amd.com; helo=NAM10-BN7-obe.outbound.protection.outlook.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.145, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1718974844943100005 Content-Type: text/plain; charset="utf-8" Read boot-mode value as machine property and propagate that to SLCR.BOOT_MODE register. Signed-off-by: Sai Pavan Boddu Acked-by: Edgar E. Iglesias Reviewed-by: Francisco Iglesias --- hw/arm/xilinx_zynq.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index 7f7a3d23fbe..97b6fd8e35d 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -38,6 +38,7 @@ #include "qom/object.h" #include "exec/tswap.h" #include "target/arm/cpu-qom.h" +#include "qapi/visitor.h" =20 #define TYPE_ZYNQ_MACHINE MACHINE_TYPE_NAME("xilinx-zynq-a9") OBJECT_DECLARE_SIMPLE_TYPE(ZynqMachineState, ZYNQ_MACHINE) @@ -90,6 +91,7 @@ struct ZynqMachineState { MachineState parent; Clock *ps_clk; ARMCPU *cpu[ZYNQ_MAX_CPUS]; + uint8_t boot_mode; }; =20 static void zynq_write_board_setup(ARMCPU *cpu, @@ -176,6 +178,27 @@ static inline int zynq_init_spi_flashes(uint32_t base_= addr, qemu_irq irq, return unit; } =20 +static void zynq_set_boot_mode(Object *obj, const char *str, + Error **errp) +{ + ZynqMachineState *m =3D ZYNQ_MACHINE(obj); + uint8_t mode =3D 0; + + if (!strncasecmp(str, "qspi", 4)) { + mode =3D 1; + } else if (!strncasecmp(str, "sd", 2)) { + mode =3D 5; + } else if (!strncasecmp(str, "nor", 3)) { + mode =3D 2; + } else if (!strncasecmp(str, "jtag", 4)) { + mode =3D 0; + } else { + error_setg(errp, "%s boot mode not supported", str); + return; + } + m->boot_mode =3D mode; +} + static void zynq_init(MachineState *machine) { ZynqMachineState *zynq_machine =3D ZYNQ_MACHINE(machine); @@ -241,6 +264,7 @@ static void zynq_init(MachineState *machine) /* Create slcr, keep a pointer to connect clocks */ slcr =3D qdev_new("xilinx-zynq_slcr"); qdev_connect_clock_in(slcr, "ps_clk", zynq_machine->ps_clk); + qdev_prop_set_uint8(slcr, "boot-mode", zynq_machine->boot_mode); sysbus_realize_and_unref(SYS_BUS_DEVICE(slcr), &error_fatal); sysbus_mmio_map(SYS_BUS_DEVICE(slcr), 0, 0xF8000000); =20 @@ -372,6 +396,7 @@ static void zynq_machine_class_init(ObjectClass *oc, vo= id *data) NULL }; MachineClass *mc =3D MACHINE_CLASS(oc); + ObjectProperty *prop; mc->desc =3D "Xilinx Zynq Platform Baseboard for Cortex-A9"; mc->init =3D zynq_init; mc->max_cpus =3D ZYNQ_MAX_CPUS; @@ -379,6 +404,12 @@ static void zynq_machine_class_init(ObjectClass *oc, v= oid *data) mc->ignore_memory_transaction_failures =3D true; mc->valid_cpu_types =3D valid_cpu_types; mc->default_ram_id =3D "zynq.ext_ram"; + prop =3D object_class_property_add_str(oc, "boot-mode", NULL, + zynq_set_boot_mode); + object_class_property_set_description(oc, "boot-mode", + "Supported boot modes:" + " jtag qspi sd nor"); + object_property_set_default_str(prop, "qspi"); } =20 static const TypeInfo zynq_machine_type =3D { --=20 2.34.1 From nobody Mon Nov 25 01:30:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=amd.com); dmarc=pass(p=quarantine dis=none) header.from=amd.com ARC-Seal: i=2; a=rsa-sha256; t=1718974808; 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Iglesias'" , Peter Maydell , , , "Edgar E . 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Signed-off-by: Sai Pavan Boddu Reviewed-by: Edgar E. Iglesias Reviewed-by: Francisco Iglesias --- MAINTAINERS | 1 + docs/system/arm/xlnx-zynq.rst | 47 +++++++++++++++++++++++++++++++++++ docs/system/target-arm.rst | 1 + 3 files changed, 49 insertions(+) create mode 100644 docs/system/arm/xlnx-zynq.rst diff --git a/MAINTAINERS b/MAINTAINERS index 951556224a1..2f06febc676 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1033,6 +1033,7 @@ F: hw/adc/zynq-xadc.c F: include/hw/misc/zynq_slcr.h F: include/hw/adc/zynq-xadc.h X: hw/ssi/xilinx_* +F: docs/system/arm/xlnx-zynq.rst =20 Xilinx ZynqMP and Versal M: Alistair Francis diff --git a/docs/system/arm/xlnx-zynq.rst b/docs/system/arm/xlnx-zynq.rst new file mode 100644 index 00000000000..ade18a3fe13 --- /dev/null +++ b/docs/system/arm/xlnx-zynq.rst @@ -0,0 +1,47 @@ +Xilinx Zynq board (``xilinx-zynq-a9``) +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +The Zynq 7000 family is based on the AMD SoC architecture. These products +integrate a feature-rich dual or single-core Arm Cortex-A9 MPCore based +processing system (PS) and AMD programmable logic (PL) in a single device. + +More details here: +https://docs.amd.com/r/en-US/ug585-zynq-7000-SoC-TRM/Zynq-7000-SoC-Technic= al-Reference-Manual + +QEMU xilinx-zynq-a9 board supports following devices: + - A9 MPCORE + - cortex-a9 + - GIC v1 + - Generic timer + - wdt + - OCM 256KB + - SMC SRAM@0xe2000000 64MB + - Zynq SLCR + - SPI x2 + - QSPI + - UART + - TTC x2 + - Gigabit Ethernet Controller x2 + - SD Controller x2 + - XADC + - Arm PrimeCell DMA Controller + - DDR Memory + - USB 2.0 x2 + +Running +""""""" +Direct Linux boot of a generic ARM upstream Linux kernel: + +.. code-block:: bash + + $ qemu-system-aarch64 -M xilinx-zynq-a9 \ + -dtb zynq-zc702.dtb -serial null -serial mon:stdio \ + -display none -m 1024 \ + -initrd rootfs.cpio.gz -kernel zImage + +For configuring the boot-mode provide the following on the command line: + +.. code-block:: bash + + -machine boot-mode=3Dqspi + +Supported values are jtag, sd, qspi, nor. diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst index 870d30e3502..7b992722846 100644 --- a/docs/system/target-arm.rst +++ b/docs/system/target-arm.rst @@ -109,6 +109,7 @@ undocumented; you can get a complete list by running arm/virt arm/xenpvh arm/xlnx-versal-virt + arm/xlnx-zynq =20 Emulated CPU architecture support =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D --=20 2.34.1