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[128.178.122.21]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a6f7373484esm565651066b.147.2024.06.20.07.02.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Jun 2024 07:02:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1718892178; x=1719496978; darn=nongnu.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=8JcYGEPwPru8qUDB09nHeyCS8JgDTBK2beev54WwtpQ=; b=EhoyO+hqX0IGidCKkqFgFKwtKiWksAoxM5E0SnPcQ3NoX4UcIlOFi/2RJlwBXFuuww N/RTtTlAtWB7XFU3cCt1G3wJC+o5ZxxD1KR6KxxD8JhXbXTl7JYNt97if2/j5Hd0OItL 5HM6uCVs3ZXrKYsO7cizPzHSibKkB8P+FyxmTVgBqTiW7d33wFAAM1dO0o4supH8CLTk dzzLulVh1/pEdwDxR8HTkvMjKpkRVoWsyeICn6Uco4lHbp4bIwtnWPokeuQZbn1dLfap yVK+HQekXCdAwe2q8YooYD7PTkonugI5feyHi36gZcOxQnsU3PTc6quTrQoL47JNeSG1 3O2A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1718892178; x=1719496978; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=8JcYGEPwPru8qUDB09nHeyCS8JgDTBK2beev54WwtpQ=; b=PS9pdX7HEII5ZVvHbc2LhIBSKcvFOPU0AocqjPic5X54HB/fSVNAsh26axZ/ZSjTX/ CcOsgUJfCLfFzo2VT19PVgqPo8/uwNqAzfjzSMT84TP9oZ21iJrK1j4KHuuspcUIE70W 0qKAAYobPIadIV3Izmq8KHVPgWGzdNjbmIF82bR1Ey0Z837uZJTQGOlQq3HfmuI5co0h H0+BUQvy0adT6AYzTw9xSIrFh45oisXi7GdkwPQj3Kq6TpiqUT8hdCfLH+0RecfWyk7t H/x5AOR7A3TjMu0bMiye5iYKYw2c8k0tsy7yrjGLdDSM6v1lk58w+0ME9OJTzQ2msl/h 76Wg== X-Forwarded-Encrypted: i=1; AJvYcCW7A1ONBGkR0Y2nyAAn4xxc89So1evn5cQKH+zDdjLUQJUJVbyL15DGoE6FKPiUWO6dX4XudDeOs6ULMceNdH51aw2CTJ+cNYP/GMrTE8UAIdjR+6cJ3d9t1g8= X-Gm-Message-State: AOJu0YwteDs+C0QgXdRJUvf6VvZ30N/cpQiVgNOIF1KFopZl2u37eMWB 7PZMKJ8VM2uWNvYwNiOkspoFfiOJrTE8pqCxBkNbNkg83SvB10yvlFJ+zhA= X-Google-Smtp-Source: AGHT+IHLG4GyZnsQbN9k+BhJLuuN6BWZ1AbPaSdwFMhtSHRFul3HQYBEIdag/MWEIy3XV5KvK3nDtg== X-Received: by 2002:a17:906:9c18:b0:a6f:3e20:bf15 with SMTP id a640c23a62f3a-a6fab62a235mr305046666b.31.1718892177839; Thu, 20 Jun 2024 07:02:57 -0700 (PDT) From: Zheyu Ma To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Andrew Jeffery , Joel Stanley Cc: Zheyu Ma , qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v4] hw/gpio/aspeed: Add reg_table_count to AspeedGPIOClass Date: Thu, 20 Jun 2024 16:02:39 +0200 Message-Id: <20240620140239.375338-1-zheyuma97@gmail.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::62c; envelope-from=zheyuma97@gmail.com; helo=mail-ej1-x62c.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1718892196535100001 Content-Type: text/plain; charset="utf-8" ASan detected a global-buffer-overflow error in the aspeed_gpio_read() function. This issue occurred when reading beyond the bounds of the reg_table. To enhance the safety and maintainability of the Aspeed GPIO code, this com= mit introduces a reg_table_count member to the AspeedGPIOClass structure. This change ensures that the size of the GPIO register table is explicitly track= ed and initialized, reducing the risk of errors if new register tables are introduced in the future. Reproducer: cat << EOF | qemu-system-aarch64 -display none \ -machine accel=3Dqtest, -m 512M -machine ast1030-evb -qtest stdio readq 0x7e780272 EOF ASAN log indicating the issue: =3D=3D2602930=3D=3DERROR: AddressSanitizer: global-buffer-overflow on addre= ss 0x55a5da29e128 at pc 0x55a5d700dc62 bp 0x7fff096c4e90 sp 0x7fff096c4e88 READ of size 2 at 0x55a5da29e128 thread T0 #0 0x55a5d700dc61 in aspeed_gpio_read hw/gpio/aspeed_gpio.c:564:14 #1 0x55a5d933f3ab in memory_region_read_accessor system/memory.c:445:11 #2 0x55a5d92fba40 in access_with_adjusted_size system/memory.c:573:18 #3 0x55a5d92f842c in memory_region_dispatch_read1 system/memory.c:1426:= 16 #4 0x55a5d92f7b68 in memory_region_dispatch_read system/memory.c:1459:9 #5 0x55a5d9376ad1 in flatview_read_continue_step system/physmem.c:2836:= 18 #6 0x55a5d9376399 in flatview_read_continue system/physmem.c:2877:19 #7 0x55a5d93775b8 in flatview_read system/physmem.c:2907:12 Signed-off-by: Zheyu Ma Reviewed-by: Andrew Jeffery Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- Changes in v4: - Change the variable name to 'reg_table_count' - Change the 'reg_table_count' type to unsigned Changes in v3: - Add the reproducer --- hw/gpio/aspeed_gpio.c | 17 +++++++++++++++++ include/hw/gpio/aspeed_gpio.h | 1 + 2 files changed, 18 insertions(+) diff --git a/hw/gpio/aspeed_gpio.c b/hw/gpio/aspeed_gpio.c index c1781e2ba3..6474bb8de5 100644 --- a/hw/gpio/aspeed_gpio.c +++ b/hw/gpio/aspeed_gpio.c @@ -559,6 +559,12 @@ static uint64_t aspeed_gpio_read(void *opaque, hwaddr = offset, uint32_t size) return debounce_value; } =20 + if (idx >=3D agc->reg_table_count) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: idx 0x%" PRIx64 " out of bound= s\n", + __func__, idx); + return 0; + } + reg =3D &agc->reg_table[idx]; if (reg->set_idx >=3D agc->nr_gpio_sets) { qemu_log_mask(LOG_GUEST_ERROR, "%s: no getter for offset 0x%" @@ -785,6 +791,12 @@ static void aspeed_gpio_write(void *opaque, hwaddr off= set, uint64_t data, return; } =20 + if (idx >=3D agc->reg_table_count) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: idx 0x%" PRIx64 " out of bound= s\n", + __func__, idx); + return; + } + reg =3D &agc->reg_table[idx]; if (reg->set_idx >=3D agc->nr_gpio_sets) { qemu_log_mask(LOG_GUEST_ERROR, "%s: no setter for offset 0x%" @@ -1117,6 +1129,7 @@ static void aspeed_gpio_ast2400_class_init(ObjectClas= s *klass, void *data) agc->nr_gpio_pins =3D 216; agc->nr_gpio_sets =3D 7; agc->reg_table =3D aspeed_3_3v_gpios; + agc->reg_table_count =3D GPIO_3_3V_REG_ARRAY_SIZE; } =20 static void aspeed_gpio_2500_class_init(ObjectClass *klass, void *data) @@ -1127,6 +1140,7 @@ static void aspeed_gpio_2500_class_init(ObjectClass *= klass, void *data) agc->nr_gpio_pins =3D 228; agc->nr_gpio_sets =3D 8; agc->reg_table =3D aspeed_3_3v_gpios; + agc->reg_table_count =3D GPIO_3_3V_REG_ARRAY_SIZE; } =20 static void aspeed_gpio_ast2600_3_3v_class_init(ObjectClass *klass, void *= data) @@ -1137,6 +1151,7 @@ static void aspeed_gpio_ast2600_3_3v_class_init(Objec= tClass *klass, void *data) agc->nr_gpio_pins =3D 208; agc->nr_gpio_sets =3D 7; agc->reg_table =3D aspeed_3_3v_gpios; + agc->reg_table_count =3D GPIO_3_3V_REG_ARRAY_SIZE; } =20 static void aspeed_gpio_ast2600_1_8v_class_init(ObjectClass *klass, void *= data) @@ -1147,6 +1162,7 @@ static void aspeed_gpio_ast2600_1_8v_class_init(Objec= tClass *klass, void *data) agc->nr_gpio_pins =3D 36; agc->nr_gpio_sets =3D 2; agc->reg_table =3D aspeed_1_8v_gpios; + agc->reg_table_count =3D GPIO_1_8V_REG_ARRAY_SIZE; } =20 static void aspeed_gpio_1030_class_init(ObjectClass *klass, void *data) @@ -1157,6 +1173,7 @@ static void aspeed_gpio_1030_class_init(ObjectClass *= klass, void *data) agc->nr_gpio_pins =3D 151; agc->nr_gpio_sets =3D 6; agc->reg_table =3D aspeed_3_3v_gpios; + agc->reg_table_count =3D GPIO_3_3V_REG_ARRAY_SIZE; } =20 static const TypeInfo aspeed_gpio_info =3D { diff --git a/include/hw/gpio/aspeed_gpio.h b/include/hw/gpio/aspeed_gpio.h index 904eecf62c..90a12ae318 100644 --- a/include/hw/gpio/aspeed_gpio.h +++ b/include/hw/gpio/aspeed_gpio.h @@ -75,6 +75,7 @@ struct AspeedGPIOClass { uint32_t nr_gpio_pins; uint32_t nr_gpio_sets; const AspeedGPIOReg *reg_table; + unsigned reg_table_count; }; =20 struct AspeedGPIOState { --=20 2.34.1