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Iglesias'" , Peter Maydell , , "Edgar E . Iglesias" Subject: [PATCH v3 1/3] hw/misc/zynq_slcr: Add boot-mode property Date: Thu, 20 Jun 2024 16:11:37 +0530 Message-ID: <20240620104139.217908-2-sai.pavan.boddu@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240620104139.217908-1-sai.pavan.boddu@amd.com> References: <20240620104139.217908-1-sai.pavan.boddu@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: None (SATLEXMB05.amd.com: sai.pavan.boddu@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000042A7:EE_|PH7PR12MB7818:EE_ X-MS-Office365-Filtering-Correlation-Id: 661a38b3-3bdd-4201-bde8-08dc91159895 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230037|1800799021|82310400023|36860700010|376011; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?M0rzBIpGCAIeYfsPU9oYhG7pKnE1bUGmZeYVYgGD/uLUefo7VBnwVRLpJuP/?= =?us-ascii?Q?babykBshBPy6rbVa7CZepe2cft98RLqQ6QjmgYPlzTheACM6n6c4RPds+0NL?= =?us-ascii?Q?c6Mg/tanRo3sE1l+gXqfzG/bcumsFkeTEHG2Oh+WI2BOqWzVdJBhnZCIpDTI?= =?us-ascii?Q?TqNMQOjBBmi2nnmXKbwAMlgA81v0hJ1apHix1fVqpkByh8XA+lQws3qLL3it?= =?us-ascii?Q?jVepkM9KOOCdH0XxTUAhltQWX+hzGR914kaazhE9tKgI6CfPGYckhy4a+evj?= =?us-ascii?Q?Z9KBXYAdqEMkLjGdmpkIfQvhGoFS03Isi4E3G3w2eWBdtWCuEYBh8zcDFzLF?= =?us-ascii?Q?je4uVr5QUTOjkFXYTLdjFoCiTnxXyQbUiegPG/wn55D3vZJYFc2JQ0JRQN5k?= =?us-ascii?Q?+H1Z9Hr32X8Cd07OuAAXGCC++uNKZaaGLzdpF+gyugkO8f679EMLH8Rl5PN7?= =?us-ascii?Q?93ZhmGOR21FGNPofXxI8SVTLBUHOy30czNVxfo0TkhY/JV3bhXf5zZYK9qRq?= =?us-ascii?Q?iTdoGG8bLEEXrYpC4VbgnsV76n56RCv5RtWrHY8ZzjJdyX5U/eVJiBpLVfdj?= =?us-ascii?Q?Va90bijAScAa6xlzHqQltTqMQmCuM4MowqTN0/WJ5+FsyB81UCRNWIsB6C6O?= =?us-ascii?Q?FVVAq4abIaGXyKPW5hnIIx6O/E92HmZ7aJIj/+68hvcIxsPWOk7TNfl2bTGE?= =?us-ascii?Q?nTlbXBmKkTpzUAk6oPq2mjzVy23khhq5Wb4ES/SjPRkHFdenSumTa30ucUjg?= =?us-ascii?Q?dzO0FppUEuC0S4u6DedfZL2qbH+J45ksYxVxIH5/PfOAu4y3iWFXGjObEC2/?= =?us-ascii?Q?7108DmwNneqaVwsGPtdvXwSpKTVOeIE7TLGZuFJ4CaT5zf1x10ufahayJDzZ?= =?us-ascii?Q?7AKUNwc+BS7eNDlJu3cTovoFr0a5yrR+kP8gqFpkANvSka5wso72puqHPkar?= =?us-ascii?Q?nN1iA0jv5JHvaAINB0QFlbPAiDLs36HZnnAhdP+T6alDuEVWAlnrMmPEDzHt?= =?us-ascii?Q?G6fNH1pz1e554w8zBtDMDe/rwAPofZJKAJSOw0984EE04c47U+njaChx0q38?= =?us-ascii?Q?KgTs9JAfGs94QjkQ8pu13EIDSeuaXxkR0p6MDoWZ7v1Oq5GoRnMvEC1AT+Ou?= =?us-ascii?Q?kM5sFuJPwZ5ITZ2t7AMd1TZCZYVfGBlJUjgRxvUT7bBihwC8ASkvfHQEMvTN?= =?us-ascii?Q?accezW6jKhxnD0sMQkSr2VnYqlBAxrA7PEFXf4OgXVo8L0Je1xw4UZEK2Kl3?= =?us-ascii?Q?HbXgFQ34WUaimMCFusrmALhsxXTuZz+08F4cbc91uAYCbdXfsax6N6qUKoTN?= =?us-ascii?Q?rsKHly286v7wqQ/yS7uaG3198bcheihwhA36LJU09vxqLKzvS9eGqWNb7xl8?= =?us-ascii?Q?PEPF7qA9IMRdqxKy+Lj5FaDkm6NHBiTCDG9o2QEStnaKcHby2w=3D=3D?= X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB03.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230037)(1800799021)(82310400023)(36860700010)(376011); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Jun 2024 10:41:51.8340 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 661a38b3-3bdd-4201-bde8-08dc91159895 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000042A7.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7818 Received-SPF: permerror client-ip=2a01:111:f403:2414::625; envelope-from=sai.pavan.boddu@amd.com; helo=NAM11-BN8-obe.outbound.protection.outlook.com X-Spam_score_int: -22 X-Spam_score: -2.3 X-Spam_bar: -- X-Spam_report: (-2.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.144, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1718880205030100001 Content-Type: text/plain; charset="utf-8" boot-mode property sets user values into BOOT_MODE register, on hardware these are derived from board switches. Signed-off-by: Sai Pavan Boddu Reviewed-by: Edgar E. Iglesias Reviewed-by: Francisco Iglesias --- hw/misc/zynq_slcr.c | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/hw/misc/zynq_slcr.c b/hw/misc/zynq_slcr.c index 3412ff099ea..ad814c3a79b 100644 --- a/hw/misc/zynq_slcr.c +++ b/hw/misc/zynq_slcr.c @@ -24,6 +24,8 @@ #include "hw/registerfields.h" #include "hw/qdev-clock.h" #include "qom/object.h" +#include "hw/qdev-properties.h" +#include "qapi/error.h" =20 #ifndef ZYNQ_SLCR_ERR_DEBUG #define ZYNQ_SLCR_ERR_DEBUG 0 @@ -121,6 +123,7 @@ REG32(RST_REASON, 0x250) =20 REG32(REBOOT_STATUS, 0x258) REG32(BOOT_MODE, 0x25c) + FIELD(BOOT_MODE, BOOT_MODE, 0, 4) =20 REG32(APU_CTRL, 0x300) REG32(WDT_CLK_SEL, 0x304) @@ -195,6 +198,7 @@ struct ZynqSLCRState { Clock *ps_clk; Clock *uart0_ref_clk; Clock *uart1_ref_clk; + uint8_t boot_mode; }; =20 /* @@ -371,7 +375,7 @@ static void zynq_slcr_reset_init(Object *obj, ResetType= type) s->regs[R_FPGA_RST_CTRL] =3D 0x01F33F0F; s->regs[R_RST_REASON] =3D 0x00000040; =20 - s->regs[R_BOOT_MODE] =3D 0x00000001; + s->regs[R_BOOT_MODE] =3D s->boot_mode & R_BOOT_MODE_BOOT_MODE_MAS= K; =20 /* 0x700 - 0x7D4 */ for (i =3D 0; i < 54; i++) { @@ -588,6 +592,15 @@ static const ClockPortInitArray zynq_slcr_clocks =3D { QDEV_CLOCK_END }; =20 +static void zynq_slcr_realize(DeviceState *dev, Error **errp) +{ + ZynqSLCRState *s =3D ZYNQ_SLCR(dev); + + if (s->boot_mode > 0xF) { + error_setg(errp, "Invalid boot mode %d specified", s->boot_mode); + } +} + static void zynq_slcr_init(Object *obj) { ZynqSLCRState *s =3D ZYNQ_SLCR(obj); @@ -610,15 +623,22 @@ static const VMStateDescription vmstate_zynq_slcr =3D= { } }; =20 +static Property zynq_slcr_props[] =3D { + DEFINE_PROP_UINT8("boot-mode", ZynqSLCRState, boot_mode, 1), + DEFINE_PROP_END_OF_LIST(), +}; + static void zynq_slcr_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); ResettableClass *rc =3D RESETTABLE_CLASS(klass); =20 dc->vmsd =3D &vmstate_zynq_slcr; + dc->realize =3D zynq_slcr_realize; rc->phases.enter =3D zynq_slcr_reset_init; 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Iglesias'" , Peter Maydell , , "Edgar E . Iglesias" Subject: [PATCH v3 2/3] hw/arm/xilinx_zynq: Add boot-mode property Date: Thu, 20 Jun 2024 16:11:38 +0530 Message-ID: <20240620104139.217908-3-sai.pavan.boddu@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240620104139.217908-1-sai.pavan.boddu@amd.com> References: <20240620104139.217908-1-sai.pavan.boddu@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: None (SATLEXMB03.amd.com: sai.pavan.boddu@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000042A7:EE_|DM4PR12MB5964:EE_ X-MS-Office365-Filtering-Correlation-Id: cb6fabd8-7b78-4dc0-0b4f-08dc91159a69 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230037|376011|36860700010|1800799021|82310400023; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?QCsz2uJzPxrTRGLarSuzP3Gty7LOLT3bwmCuiHTvfOY1VsNLq7ZsNLv1vrAz?= =?us-ascii?Q?xFJ5B0zHkPK81rb+1/3T96BTSQ5CV3FOyiJQ30OHI1oWQ5xMAeNVFKdHXFgH?= =?us-ascii?Q?tNVIsnyV2mZ0I5KPeO1Dv9jB6D7Guxe1J5CmPPChsg5HTsXMmkdvxug/F9kk?= =?us-ascii?Q?NrPifRNe2Uicz6s4rVbEfJ3onoD2kzgbdNIQDDtoep8RTDDwMQdx8/Wms8fi?= =?us-ascii?Q?Mtue90ljG4hwZ/G2Jj8XquCX8tW7yUB0GmbL9yu10zUFiDvdP1qLB+FZNpVa?= =?us-ascii?Q?eoqZmBnKV2mSHPnOVdwYqbonvpduzTRWLA5+t19G/OukRb5/e+ScoFjKkONP?= =?us-ascii?Q?8fs1IkPryOvs7W+qG7gXzaQotezdqJjdkJAW7p8ioP484PKKAMaqZ8HkitPE?= =?us-ascii?Q?hma2gFNhoFY3CLckHPS/yz++93JUJbrqBkDHYvI1Sqz40Zx3dDvqWgOMyjJn?= =?us-ascii?Q?tp5p3W03VfsqIAlv+wYnS3ZAgvsw4VsboM5tKWafiZa3HgbRsMHJon4HsY6u?= =?us-ascii?Q?6sp7ti8teyF3DEJ0SV8v/E9H2aL+iQxkZUT5IiB/gW46IduK77i9QzjhKmMh?= =?us-ascii?Q?3tXDd6YoRCNiQq4wZrSx/bY7atl6PWkUtSBKnpSXHYt/O9UehU7IwyNDGShn?= =?us-ascii?Q?WT2jspTZ0+K49aCXDJ35IPNr2jrP+kxkdadV9leegUeLmjANYWm4K7HEXHBX?= =?us-ascii?Q?CeKKuTegXOrZvnvCm+v2jRTANbLNWWsGS8wVWFB7wlXAd8MPIq4eaB9iyR4W?= =?us-ascii?Q?9VP3S02r7h1XovumbB0EF48vNxwLMwQDrnL6EkpUsLF7+7LYme0BBEiIkXaJ?= =?us-ascii?Q?I1V27xpjGJnQzuUcoGPnIxBA1RzXvKjvx3tTFbSed0iaC9MRXNaxAwTFyMrz?= =?us-ascii?Q?fZPCPNXhWm+gAS7tGpV9bZNeLn2q8Z8/K9Yp25gLeWvFsebALOl7UXkRE8q8?= =?us-ascii?Q?q/xgOGf+UuawnkDrO/c2+uK1dgAjP1MPl0ttA3e2PJ1V6CTjOhuTLHIiUPHX?= =?us-ascii?Q?7dozkbZ6aQibUpRuM01Y3eJreKosv7Db6xk+Qnw15MtyvHTBHsivylIAO1xV?= =?us-ascii?Q?wxAiN0ypeNTjYFxnlPmgQWNeqjicJC/X2JOPdYUhfsKGSdnKIa2mPjExtFF4?= =?us-ascii?Q?l5mhfg17ZrO4bsiXDc4AwT/zfaxZ02qibi5bLlz2qqTDWMZslCuxkMdZ+7nO?= =?us-ascii?Q?QZMHFuOGdIW0+VTluJCoDNU+LGqba2uXLvKhn2HE8xAs8e4lFb/UzXyOPV5i?= =?us-ascii?Q?VaHAoChvYznkmkNAHOM6xOKmiwpTsueC9Vg4nfN3fQNEm7BwwURRMF9oqD8W?= =?us-ascii?Q?EleKJHYNRQ7LYPOjxjamAiy9LDlbxIUb293MNGiXmPd39fgVaIFgHVIkaJtH?= =?us-ascii?Q?nS+hXDcgsuije1J6gKOyLZgw2pIdMp94Dlx0AmlXiwIVsuYlsQ=3D=3D?= X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB03.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230037)(376011)(36860700010)(1800799021)(82310400023); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Jun 2024 10:41:54.8496 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cb6fabd8-7b78-4dc0-0b4f-08dc91159a69 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000042A7.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5964 Received-SPF: permerror client-ip=2a01:111:f403:2414::605; envelope-from=sai.pavan.boddu@amd.com; helo=NAM11-BN8-obe.outbound.protection.outlook.com X-Spam_score_int: -22 X-Spam_score: -2.3 X-Spam_bar: -- X-Spam_report: (-2.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.144, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1718880189083100004 Content-Type: text/plain; charset="utf-8" Read boot-mode value as machine property and propagate that to SLCR.BOOT_MODE register. Signed-off-by: Sai Pavan Boddu Acked-by: Edgar E. Iglesias Reviewed-by: Francisco Iglesias --- hw/arm/xilinx_zynq.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index 7f7a3d23fbe..39f07e6dfd8 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -38,6 +38,7 @@ #include "qom/object.h" #include "exec/tswap.h" #include "target/arm/cpu-qom.h" +#include "qapi/visitor.h" =20 #define TYPE_ZYNQ_MACHINE MACHINE_TYPE_NAME("xilinx-zynq-a9") OBJECT_DECLARE_SIMPLE_TYPE(ZynqMachineState, ZYNQ_MACHINE) @@ -90,6 +91,7 @@ struct ZynqMachineState { MachineState parent; Clock *ps_clk; ARMCPU *cpu[ZYNQ_MAX_CPUS]; + uint8_t boot_mode; }; =20 static void zynq_write_board_setup(ARMCPU *cpu, @@ -176,6 +178,27 @@ static inline int zynq_init_spi_flashes(uint32_t base_= addr, qemu_irq irq, return unit; } =20 +static void zynq_set_boot_mode(Object *obj, const char *str, + Error **errp) +{ + ZynqMachineState *m =3D ZYNQ_MACHINE(obj); + uint8_t mode =3D 0; + + if (!strcasecmp(str, "QSPI")) { + mode =3D 1; + } else if (!strcasecmp(str, "SD")) { + mode =3D 5; + } else if (!strcasecmp(str, "NOR")) { + mode =3D 2; + } else if (!strcasecmp(str, "JTAG")) { + mode =3D 0; + } else { + error_setg(errp, "bootmode %s not supported", str); + return; + } + m->boot_mode =3D mode; +} + static void zynq_init(MachineState *machine) { ZynqMachineState *zynq_machine =3D ZYNQ_MACHINE(machine); @@ -241,6 +264,7 @@ static void zynq_init(MachineState *machine) /* Create slcr, keep a pointer to connect clocks */ slcr =3D qdev_new("xilinx-zynq_slcr"); qdev_connect_clock_in(slcr, "ps_clk", zynq_machine->ps_clk); + qdev_prop_set_uint8(slcr, "boot-mode", zynq_machine->boot_mode); sysbus_realize_and_unref(SYS_BUS_DEVICE(slcr), &error_fatal); sysbus_mmio_map(SYS_BUS_DEVICE(slcr), 0, 0xF8000000); =20 @@ -372,6 +396,7 @@ static void zynq_machine_class_init(ObjectClass *oc, vo= id *data) NULL }; MachineClass *mc =3D MACHINE_CLASS(oc); + ObjectProperty *prop; mc->desc =3D "Xilinx Zynq Platform Baseboard for Cortex-A9"; mc->init =3D zynq_init; mc->max_cpus =3D ZYNQ_MAX_CPUS; @@ -379,6 +404,12 @@ static void zynq_machine_class_init(ObjectClass *oc, v= oid *data) mc->ignore_memory_transaction_failures =3D true; mc->valid_cpu_types =3D valid_cpu_types; mc->default_ram_id =3D "zynq.ext_ram"; + prop =3D object_class_property_add_str(oc, "boot-mode", NULL, + zynq_set_boot_mode); + object_class_property_set_description(oc, "boot-mode", + "Supported boot modes:" + " JTAG QSPI SD NOR"); + object_property_set_default_str(prop, "QSPI"); } =20 static const TypeInfo zynq_machine_type =3D { --=20 2.34.1 From nobody Mon Nov 25 00:34:28 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=amd.com); dmarc=pass(p=quarantine dis=none) header.from=amd.com ARC-Seal: i=2; a=rsa-sha256; t=1718880190; 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Iglesias'" , Peter Maydell , , "Edgar E . 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Signed-off-by: Sai Pavan Boddu Reviewed-by: Edgar E. Iglesias Reviewed-by: Francisco Iglesias --- MAINTAINERS | 1 + docs/system/arm/xlnx-zynq.rst | 47 +++++++++++++++++++++++++++++++++++ docs/system/target-arm.rst | 1 + 3 files changed, 49 insertions(+) create mode 100644 docs/system/arm/xlnx-zynq.rst diff --git a/MAINTAINERS b/MAINTAINERS index 951556224a1..2f06febc676 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1033,6 +1033,7 @@ F: hw/adc/zynq-xadc.c F: include/hw/misc/zynq_slcr.h F: include/hw/adc/zynq-xadc.h X: hw/ssi/xilinx_* +F: docs/system/arm/xlnx-zynq.rst =20 Xilinx ZynqMP and Versal M: Alistair Francis diff --git a/docs/system/arm/xlnx-zynq.rst b/docs/system/arm/xlnx-zynq.rst new file mode 100644 index 00000000000..ade18a3fe13 --- /dev/null +++ b/docs/system/arm/xlnx-zynq.rst @@ -0,0 +1,47 @@ +Xilinx Zynq board (``xilinx-zynq-a9``) +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +The Zynq 7000 family is based on the AMD SoC architecture. These products +integrate a feature-rich dual or single-core Arm Cortex-A9 MPCore based +processing system (PS) and AMD programmable logic (PL) in a single device. + +More details here: +https://docs.amd.com/r/en-US/ug585-zynq-7000-SoC-TRM/Zynq-7000-SoC-Technic= al-Reference-Manual + +QEMU xilinx-zynq-a9 board supports following devices: + - A9 MPCORE + - cortex-a9 + - GIC v1 + - Generic timer + - wdt + - OCM 256KB + - SMC SRAM@0xe2000000 64MB + - Zynq SLCR + - SPI x2 + - QSPI + - UART + - TTC x2 + - Gigabit Ethernet Controller x2 + - SD Controller x2 + - XADC + - Arm PrimeCell DMA Controller + - DDR Memory + - USB 2.0 x2 + +Running +""""""" +Direct Linux boot of a generic ARM upstream Linux kernel: + +.. code-block:: bash + + $ qemu-system-aarch64 -M xilinx-zynq-a9 \ + -dtb zynq-zc702.dtb -serial null -serial mon:stdio \ + -display none -m 1024 \ + -initrd rootfs.cpio.gz -kernel zImage + +For configuring the boot-mode provide the following on the command line: + +.. code-block:: bash + + -machine boot-mode=3Dqspi + +Supported values are jtag, sd, qspi, nor. diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst index 870d30e3502..7b992722846 100644 --- a/docs/system/target-arm.rst +++ b/docs/system/target-arm.rst @@ -109,6 +109,7 @@ undocumented; you can get a complete list by running arm/virt arm/xenpvh arm/xlnx-versal-virt + arm/xlnx-zynq =20 Emulated CPU architecture support =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D --=20 2.34.1