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Date: Wed, 19 Jun 2024 16:27:07 +0100 Message-Id: <20240619152708.135991-6-rkanwal@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240619152708.135991-1-rkanwal@rivosinc.com> References: <20240619152708.135991-1-rkanwal@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=rkanwal@rivosinc.com; helo=mail-pl1-x62a.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1718810903317100001 Content-Type: text/plain; charset="utf-8" CTR extension adds a new instruction sctrclr to quickly clear the recorded entries buffer. Signed-off-by: Rajnesh Kanwal --- target/riscv/cpu.h | 1 + target/riscv/cpu_helper.c | 7 ++++ target/riscv/helper.h | 1 + target/riscv/insn32.decode | 1 + .../riscv/insn_trans/trans_privileged.c.inc | 10 ++++++ target/riscv/op_helper.c | 33 +++++++++++++++++++ 6 files changed, 53 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index e32f5ab146..fdc18a782a 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -572,6 +572,7 @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ulon= g newpriv, bool virt_en); void riscv_ctr_freeze(CPURISCVState *env, uint64_t freeze_mask, bool virt); void riscv_ctr_add_entry(CPURISCVState *env, target_long src, target_long = dst, uint64_t type, target_ulong prev_priv, bool prev_= virt); +void riscv_ctr_clear(CPURISCVState *env); =20 void riscv_translate_init(void); G_NORETURN void riscv_raise_exception(CPURISCVState *env, diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 1537602e1b..d98628cfe3 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -702,6 +702,13 @@ void riscv_ctr_freeze(CPURISCVState *env, uint64_t fre= eze_mask, bool virt) } } =20 +void riscv_ctr_clear(CPURISCVState *env) +{ + memset(env->ctr_src, 0x0, sizeof(env->ctr_src)); + memset(env->ctr_dst, 0x0, sizeof(env->ctr_dst)); + memset(env->ctr_data, 0x0, sizeof(env->ctr_data)); +} + static uint64_t riscv_ctr_priv_to_mask(target_ulong priv, bool virt) { switch (priv) { diff --git a/target/riscv/helper.h b/target/riscv/helper.h index b8fb7c8734..a3b2d87527 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -131,6 +131,7 @@ DEF_HELPER_6(csrrw_i128, tl, env, int, tl, tl, tl, tl) #ifndef CONFIG_USER_ONLY DEF_HELPER_2(sret, tl, env, tl) DEF_HELPER_2(mret, tl, env, tl) +DEF_HELPER_1(ctr_clear, void, env) DEF_HELPER_1(wfi, void, env) DEF_HELPER_1(wrs_nto, void, env) DEF_HELPER_1(tlb_flush, void, env) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 9cb1a1b4ec..d3d38c7c68 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -107,6 +107,7 @@ # *** Privileged Instructions *** ecall 000000000000 00000 000 00000 1110011 ebreak 000000000001 00000 000 00000 1110011 +sctrclr 000100000100 00000 000 00000 1110011 uret 0000000 00010 00000 000 00000 1110011 sret 0001000 00010 00000 000 00000 1110011 mret 0011000 00010 00000 000 00000 1110011 diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/= insn_trans/trans_privileged.c.inc index 339d659151..dd9da8651f 100644 --- a/target/riscv/insn_trans/trans_privileged.c.inc +++ b/target/riscv/insn_trans/trans_privileged.c.inc @@ -69,6 +69,16 @@ static bool trans_ebreak(DisasContext *ctx, arg_ebreak *= a) return true; } =20 +static bool trans_sctrclr(DisasContext *ctx, arg_sctrclr *a) +{ +#ifndef CONFIG_USER_ONLY + gen_helper_ctr_clear(tcg_env); + return true; +#else + return false; +#endif +} + static bool trans_uret(DisasContext *ctx, arg_uret *a) { return false; diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 5a1e92c45e..15a770360e 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -475,6 +475,39 @@ void helper_ctr_branch(CPURISCVState *env, target_ulon= g src, target_ulong dest, } } =20 +void helper_ctr_clear(CPURISCVState *env) +{ + if (!riscv_cpu_cfg(env)->ext_ssctr && !riscv_cpu_cfg(env)->ext_smctr) { + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); + } + + /* + * It's safe to call smstateen_acc_ok() for umode access regardless of= the + * state of bit 54 (CTR bit in case of m/hstateen) of sstateen. If the= bit + * is zero, smstateen_acc_ok() will return the correct exception code = and + * if it's one, smstateen_acc_ok() will return RISCV_EXCP_NONE. In that + * scenario the U-mode check below will handle that case. + */ + RISCVException ret =3D smstateen_acc_ok(env, 0, SMSTATEEN0_CTR); + if (ret !=3D RISCV_EXCP_NONE) { + riscv_raise_exception(env, ret, GETPC()); + } + + if (env->priv =3D=3D PRV_U) { + /* + * One corner case is when sctrclr is executed from VU-mode and + * mstateen.CTR =3D 0, in which case we are supposed to raise + * RISCV_EXCP_ILLEGAL_INST. This case is already handled in + * smstateen_acc_ok(). + */ + uint32_t excep =3D env->virt_enabled ? RISCV_EXCP_VIRT_INSTRUCTION= _FAULT : + RISCV_EXCP_ILLEGAL_INST; + riscv_raise_exception(env, excep, GETPC()); + } + + riscv_ctr_clear(env); +} + void helper_wfi(CPURISCVState *env) { CPUState *cs =3D env_cpu(env); --=20 2.34.1