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Signed-off-by: Sai Pavan Boddu Reviewed-by: Edgar E. Iglesias --- hw/misc/zynq_slcr.c | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/hw/misc/zynq_slcr.c b/hw/misc/zynq_slcr.c index 3412ff099ea..ad814c3a79b 100644 --- a/hw/misc/zynq_slcr.c +++ b/hw/misc/zynq_slcr.c @@ -24,6 +24,8 @@ #include "hw/registerfields.h" #include "hw/qdev-clock.h" #include "qom/object.h" +#include "hw/qdev-properties.h" +#include "qapi/error.h" =20 #ifndef ZYNQ_SLCR_ERR_DEBUG #define ZYNQ_SLCR_ERR_DEBUG 0 @@ -121,6 +123,7 @@ REG32(RST_REASON, 0x250) =20 REG32(REBOOT_STATUS, 0x258) REG32(BOOT_MODE, 0x25c) + FIELD(BOOT_MODE, BOOT_MODE, 0, 4) =20 REG32(APU_CTRL, 0x300) REG32(WDT_CLK_SEL, 0x304) @@ -195,6 +198,7 @@ struct ZynqSLCRState { Clock *ps_clk; Clock *uart0_ref_clk; Clock *uart1_ref_clk; + uint8_t boot_mode; }; =20 /* @@ -371,7 +375,7 @@ static void zynq_slcr_reset_init(Object *obj, ResetType= type) s->regs[R_FPGA_RST_CTRL] =3D 0x01F33F0F; s->regs[R_RST_REASON] =3D 0x00000040; =20 - s->regs[R_BOOT_MODE] =3D 0x00000001; + s->regs[R_BOOT_MODE] =3D s->boot_mode & R_BOOT_MODE_BOOT_MODE_MAS= K; =20 /* 0x700 - 0x7D4 */ for (i =3D 0; i < 54; i++) { @@ -588,6 +592,15 @@ static const ClockPortInitArray zynq_slcr_clocks =3D { QDEV_CLOCK_END }; =20 +static void zynq_slcr_realize(DeviceState *dev, Error **errp) +{ + ZynqSLCRState *s =3D ZYNQ_SLCR(dev); + + if (s->boot_mode > 0xF) { + error_setg(errp, "Invalid boot mode %d specified", s->boot_mode); + } +} + static void zynq_slcr_init(Object *obj) { ZynqSLCRState *s =3D ZYNQ_SLCR(obj); @@ -610,15 +623,22 @@ static const VMStateDescription vmstate_zynq_slcr =3D= { } }; =20 +static Property zynq_slcr_props[] =3D { + DEFINE_PROP_UINT8("boot-mode", ZynqSLCRState, boot_mode, 1), + DEFINE_PROP_END_OF_LIST(), +}; + static void zynq_slcr_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); ResettableClass *rc =3D RESETTABLE_CLASS(klass); =20 dc->vmsd =3D &vmstate_zynq_slcr; + dc->realize =3D zynq_slcr_realize; rc->phases.enter =3D zynq_slcr_reset_init; rc->phases.hold =3D zynq_slcr_reset_hold; rc->phases.exit =3D zynq_slcr_reset_exit; + device_class_set_props(dc, zynq_slcr_props); } =20 static const TypeInfo zynq_slcr_info =3D { --=20 2.34.1