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Mon, 17 Jun 2024 11:58:50 -0700 (PDT) From: Ajeet Singh X-Google-Original-From: Ajeet Singh To: qemu-devel@nongnu.org Cc: Warner Losh , Ajeet Singh , Ajeet Singh Subject: [PATCH 14/23] Add ARM AArch64 hardware capability definitions Date: Tue, 18 Jun 2024 00:27:55 +0530 Message-Id: <20240617185804.25075-15-itachis@FreeBSD.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240617185804.25075-1-itachis@FreeBSD.org> References: <20240617185804.25075-1-itachis@FreeBSD.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=itachis6234@gmail.com; helo=mail-pf1-x42d.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01, UPPERCASE_50_75=0.008 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1718650830441100001 Content-Type: text/plain; charset="utf-8" From: Warner Losh Defined a huge list of hardware capabilites and added macros for retrieving hwcap flags Signed-off-by: Warner Losh Signed-off-by: Ajeet Singh Acked-by: Richard Henderson --- bsd-user/aarch64/target_arch_elf.h | 61 ++++++++++++++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/bsd-user/aarch64/target_arch_elf.h b/bsd-user/aarch64/target_a= rch_elf.h index 6d0fa3525f..41afa5a9da 100644 --- a/bsd-user/aarch64/target_arch_elf.h +++ b/bsd-user/aarch64/target_arch_elf.h @@ -34,4 +34,65 @@ #define USE_ELF_CORE_DUMP #define ELF_EXEC_PAGESIZE 4096 =20 +enum { + ARM_HWCAP_A64_FP =3D 1 << 0, + ARM_HWCAP_A64_ASIMD =3D 1 << 1, + ARM_HWCAP_A64_EVTSTRM =3D 1 << 2, + ARM_HWCAP_A64_AES =3D 1 << 3, + ARM_HWCAP_A64_PMULL =3D 1 << 4, + ARM_HWCAP_A64_SHA1 =3D 1 << 5, + ARM_HWCAP_A64_SHA2 =3D 1 << 6, + ARM_HWCAP_A64_CRC32 =3D 1 << 7, + ARM_HWCAP_A64_ATOMICS =3D 1 << 8, + ARM_HWCAP_A64_FPHP =3D 1 << 9, + ARM_HWCAP_A64_ASIMDHP =3D 1 << 10, + ARM_HWCAP_A64_CPUID =3D 1 << 11, + ARM_HWCAP_A64_ASIMDRDM =3D 1 << 12, + ARM_HWCAP_A64_JSCVT =3D 1 << 13, + ARM_HWCAP_A64_FCMA =3D 1 << 14, + ARM_HWCAP_A64_LRCPC =3D 1 << 15, + ARM_HWCAP_A64_DCPOP =3D 1 << 16, + ARM_HWCAP_A64_SHA3 =3D 1 << 17, + ARM_HWCAP_A64_SM3 =3D 1 << 18, + ARM_HWCAP_A64_SM4 =3D 1 << 19, + ARM_HWCAP_A64_ASIMDDP =3D 1 << 20, + ARM_HWCAP_A64_SHA512 =3D 1 << 21, + ARM_HWCAP_A64_SVE =3D 1 << 22, + ARM_HWCAP_A64_ASIMDFHM =3D 1 << 23, + ARM_HWCAP_A64_DIT =3D 1 << 24, + ARM_HWCAP_A64_USCAT =3D 1 << 25, + ARM_HWCAP_A64_ILRCPC =3D 1 << 26, + ARM_HWCAP_A64_FLAGM =3D 1 << 27, + ARM_HWCAP_A64_SSBS =3D 1 << 28, + ARM_HWCAP_A64_SB =3D 1 << 29, + ARM_HWCAP_A64_PACA =3D 1 << 30, + ARM_HWCAP_A64_PACG =3D 1UL << 31, + + ARM_HWCAP2_A64_DCPODP =3D 1 << 0, + ARM_HWCAP2_A64_SVE2 =3D 1 << 1, + ARM_HWCAP2_A64_SVEAES =3D 1 << 2, + ARM_HWCAP2_A64_SVEPMULL =3D 1 << 3, + ARM_HWCAP2_A64_SVEBITPERM =3D 1 << 4, + ARM_HWCAP2_A64_SVESHA3 =3D 1 << 5, + ARM_HWCAP2_A64_SVESM4 =3D 1 << 6, + ARM_HWCAP2_A64_FLAGM2 =3D 1 << 7, + ARM_HWCAP2_A64_FRINT =3D 1 << 8, + ARM_HWCAP2_A64_SVEI8MM =3D 1 << 9, + ARM_HWCAP2_A64_SVEF32MM =3D 1 << 10, + ARM_HWCAP2_A64_SVEF64MM =3D 1 << 11, + ARM_HWCAP2_A64_SVEBF16 =3D 1 << 12, + ARM_HWCAP2_A64_I8MM =3D 1 << 13, + ARM_HWCAP2_A64_BF16 =3D 1 << 14, + ARM_HWCAP2_A64_DGH =3D 1 << 15, + ARM_HWCAP2_A64_RNG =3D 1 << 16, + ARM_HWCAP2_A64_BTI =3D 1 << 17, + ARM_HWCAP2_A64_MTE =3D 1 << 18, +}; + +#define ELF_HWCAP get_elf_hwcap() +#define ELF_HWCAP2 get_elf_hwcap2() + +#define GET_FEATURE_ID(feat, hwcap) \ + do { if (cpu_isar_feature(feat, cpu)) { hwcaps |=3D hwcap; } } while (= 0) + #endif /* TARGET_ARCH_ELF_H */ --=20 2.34.1