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Mon, 17 Jun 2024 01:13:24 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHN5II3gNThpq00wlwbaUQD+llh1N4RBhk4dBkUH2kfsJxThHnMLZlwerbFRb9Yp4XVtjoHqQ== X-Received: by 2002:a50:d4d8:0:b0:57c:6953:2cac with SMTP id 4fb4d7f45d1cf-57cbd67ed7dmr6232863a12.22.1718612003691; Mon, 17 Jun 2024 01:13:23 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Subject: [PULL 13/25] target/i386: convert MOV from/to CR and DR to new decoder Date: Mon, 17 Jun 2024 10:13:19 +0200 Message-ID: <20240617081319.88956-2-pbonzini@redhat.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240617081319.88956-1-pbonzini@redhat.com> References: <20240617081319.88956-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -22 X-Spam_score: -2.3 X-Spam_bar: -- X-Spam_report: (-2.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.148, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=-0.01, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1718612052568100001 Content-Type: text/plain; charset="utf-8" Complete implementation of C and D operand types, then the operations are just MOVs. Signed-off-by: Paolo Bonzini --- target/i386/tcg/decode-new.h | 1 + target/i386/tcg/translate.c | 79 -------------------------------- target/i386/tcg/decode-new.c.inc | 61 ++++++++++++++++++++++-- target/i386/tcg/emit.c.inc | 24 +++++++++- 4 files changed, 81 insertions(+), 84 deletions(-) diff --git a/target/i386/tcg/decode-new.h b/target/i386/tcg/decode-new.h index 8465717ea21..60a191ee763 100644 --- a/target/i386/tcg/decode-new.h +++ b/target/i386/tcg/decode-new.h @@ -90,6 +90,7 @@ typedef enum X86OpSize { X86_SIZE_w, /* 16-bit */ X86_SIZE_x, /* 128/256-bit, based on operand size */ X86_SIZE_y, /* 32/64-bit, based on operand size */ + X86_SIZE_y_d64, /* 32/64-bit, based on 64-bit mode */ X86_SIZE_z, /* 16-bit for 16-bit operand size, else 32-bit */ X86_SIZE_z_f64, /* 32-bit for 32-bit operand size or 64-bit mode, els= e 16-bit */ =20 diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index fcba9c155f9..4958f4c45d5 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -247,9 +247,6 @@ STUB_HELPER(outb, TCGv_env env, TCGv_i32 port, TCGv_i32= val) STUB_HELPER(outw, TCGv_env env, TCGv_i32 port, TCGv_i32 val) STUB_HELPER(outl, TCGv_env env, TCGv_i32 port, TCGv_i32 val) STUB_HELPER(rdmsr, TCGv_env env) -STUB_HELPER(read_crN, TCGv ret, TCGv_env env, TCGv_i32 reg) -STUB_HELPER(get_dr, TCGv ret, TCGv_env env, TCGv_i32 reg) -STUB_HELPER(set_dr, TCGv_env env, TCGv_i32 reg, TCGv val) STUB_HELPER(stgi, TCGv_env env) STUB_HELPER(svm_check_intercept, TCGv_env env, TCGv_i32 type) STUB_HELPER(vmload, TCGv_env env, TCGv_i32 aflag) @@ -4192,82 +4189,6 @@ static void disas_insn_old(DisasContext *s, CPUState= *cpu, int b) gen_nop_modrm(env, s, modrm); break; =20 - case 0x120: /* mov reg, crN */ - case 0x122: /* mov crN, reg */ - if (!check_cpl0(s)) { - break; - } - modrm =3D x86_ldub_code(env, s); - /* - * Ignore the mod bits (assume (modrm&0xc0)=3D=3D0xc0). - * AMD documentation (24594.pdf) and testing of Intel 386 and 486 - * processors all show that the mod bits are assumed to be 1's, - * regardless of actual values. - */ - rm =3D (modrm & 7) | REX_B(s); - reg =3D ((modrm >> 3) & 7) | REX_R(s); - switch (reg) { - case 0: - if ((prefixes & PREFIX_LOCK) && - (s->cpuid_ext3_features & CPUID_EXT3_CR8LEG)) { - reg =3D 8; - } - break; - case 2: - case 3: - case 4: - case 8: - break; - default: - goto unknown_op; - } - ot =3D (CODE64(s) ? MO_64 : MO_32); - - translator_io_start(&s->base); - if (b & 2) { - gen_svm_check_intercept(s, SVM_EXIT_WRITE_CR0 + reg); - gen_op_mov_v_reg(s, ot, s->T0, rm); - gen_helper_write_crN(tcg_env, tcg_constant_i32(reg), s->T0); - s->base.is_jmp =3D DISAS_EOB_NEXT; - } else { - gen_svm_check_intercept(s, SVM_EXIT_READ_CR0 + reg); - gen_helper_read_crN(s->T0, tcg_env, tcg_constant_i32(reg)); - gen_op_mov_reg_v(s, ot, rm, s->T0); - } - break; - - case 0x121: /* mov reg, drN */ - case 0x123: /* mov drN, reg */ - if (check_cpl0(s)) { - modrm =3D x86_ldub_code(env, s); - /* Ignore the mod bits (assume (modrm&0xc0)=3D=3D0xc0). - * AMD documentation (24594.pdf) and testing of - * intel 386 and 486 processors all show that the mod bits - * are assumed to be 1's, regardless of actual values. - */ - rm =3D (modrm & 7) | REX_B(s); - reg =3D ((modrm >> 3) & 7) | REX_R(s); - if (CODE64(s)) - ot =3D MO_64; - else - ot =3D MO_32; - if (reg >=3D 8) { - goto illegal_op; - } - if (b & 2) { - gen_svm_check_intercept(s, SVM_EXIT_WRITE_DR0 + reg); - gen_op_mov_v_reg(s, ot, s->T0, rm); - tcg_gen_movi_i32(s->tmp2_i32, reg); - gen_helper_set_dr(tcg_env, s->tmp2_i32, s->T0); - s->base.is_jmp =3D DISAS_EOB_NEXT; - } else { - gen_svm_check_intercept(s, SVM_EXIT_READ_DR0 + reg); - tcg_gen_movi_i32(s->tmp2_i32, reg); - gen_helper_get_dr(s->T0, tcg_env, s->tmp2_i32); - gen_op_mov_reg_v(s, ot, rm, s->T0); - } - } - break; case 0x106: /* clts */ if (check_cpl0(s)) { gen_svm_check_intercept(s, SVM_EXIT_WRITE_CR0); diff --git a/target/i386/tcg/decode-new.c.inc b/target/i386/tcg/decode-new.= c.inc index cd925fe3589..0f31e1f455d 100644 --- a/target/i386/tcg/decode-new.c.inc +++ b/target/i386/tcg/decode-new.c.inc @@ -151,6 +151,8 @@ X86_OP_GROUP3(op, op0, s0, 2op, s0, op1, s1, ## __VA_ARGS__) #define X86_OP_GROUPw(op, op0, s0, ...) \ X86_OP_GROUP3(op, op0, s0, None, None, None, None, ## __VA_ARGS__) +#define X86_OP_GROUPwr(op, op0, s0, op1, s1, ...) \ + X86_OP_GROUP3(op, op0, s0, op1, s1, None, None, ## __VA_ARGS__) #define X86_OP_GROUP0(op, ...) \ X86_OP_GROUP3(op, None, None, None, None, None, None, ## __VA_ARGS__) =20 @@ -985,6 +987,24 @@ static void decode_0FE6(DisasContext *s, CPUX86State *= env, X86OpEntry *entry, ui *entry =3D *decode_by_prefix(s, opcodes_0FE6); } =20 +/* + * These ignore the mod bits (assume (modrm&0xc0)=3D=3D0xc0), so group the + * pre-decode tweak here for all MOVs from/to CR and DR. + * + * AMD documentation (24594.pdf) and testing of Intel 386 and 486 + * processors all show that the mod bits are assumed to be 1's, + * regardless of actual values. + */ +static void decode_MOV_CR_DR(DisasContext *s, CPUX86State *env, X86OpEntry= *entry, uint8_t *b) +{ + /* + */ + get_modrm(s, env); + s->modrm |=3D 0xC0; + + entry->gen =3D gen_MOV; +} + static const X86OpEntry opcodes_0F[256] =3D { [0x0E] =3D X86_OP_ENTRY0(EMMS, cpuid(3DNO= W)), /* femms */ /* @@ -1004,6 +1024,15 @@ static const X86OpEntry opcodes_0F[256] =3D { /* Incorrectly listed as Mq,Vq in the manual */ [0x17] =3D X86_OP_ENTRY3(VMOVHPx_st, M,q, None,None, V,dq, vex5 p_00_= 66), =20 + /* + * Incorrectly listed as using "d" operand type in the manual. In rea= lity + * there's no 16-bit version (like y) and it does not use REX.W (like = d64). + */ + [0x20] =3D X86_OP_GROUPwr(MOV_CR_DR, R,y_d64, C,y_d64, chk(cpl0) svm= (READ_CR0)), + [0x21] =3D X86_OP_GROUPwr(MOV_CR_DR, R,y_d64, D,y_d64, chk(cpl0) svm= (READ_DR0)), + [0x22] =3D X86_OP_GROUPwr(MOV_CR_DR, C,y_d64, R,y_d64, zextT0 chk(cp= l0) svm(WRITE_CR0)), + [0x23] =3D X86_OP_GROUPwr(MOV_CR_DR, D,y_d64, R,y_d64, zextT0 chk(cp= l0) svm(WRITE_DR0)), + [0x40] =3D X86_OP_ENTRY2(CMOVcc, G,v, E,v, cpuid(CMOV)), [0x41] =3D X86_OP_ENTRY2(CMOVcc, G,v, E,v, cpuid(CMOV)), [0x42] =3D X86_OP_ENTRY2(CMOVcc, G,v, E,v, cpuid(CMOV)), @@ -1725,6 +1754,10 @@ static bool decode_op_size(DisasContext *s, X86OpEnt= ry *e, X86OpSize size, MemOp *ot =3D s->dflag =3D=3D MO_16 ? MO_32 : s->dflag; return true; =20 + case X86_SIZE_y_d64: /* Full (not 16-bit) register access */ + *ot =3D CODE64(s) ? MO_64 : MO_32; + return true; + case X86_SIZE_z: /* 16-bit for 16-bit operand size, else 32-bit */ *ot =3D s->dflag =3D=3D MO_16 ? MO_16 : MO_32; return true; @@ -1802,11 +1835,34 @@ static bool decode_op(DisasContext *s, CPUX86State = *env, X86DecodedInsn *decode, =20 case X86_TYPE_C: /* REG in the modrm byte selects a control register = */ op->unit =3D X86_OP_CR; - goto get_reg; + op->n =3D ((get_modrm(s, env) >> 3) & 7) | REX_R(s); + if (op->n =3D=3D 0 && (s->prefix & PREFIX_LOCK) && + (s->cpuid_ext3_features & CPUID_EXT3_CR8LEG)) { + op->n =3D 8; + s->prefix &=3D ~PREFIX_LOCK; + } + if (op->n !=3D 0 && op->n !=3D 2 && op->n !=3D 3 && op->n !=3D 4 &= & op->n !=3D 8) { + return false; + } + if (decode->e.intercept) { + decode->e.intercept +=3D op->n; + } + break; =20 case X86_TYPE_D: /* REG in the modrm byte selects a debug register */ op->unit =3D X86_OP_DR; - goto get_reg; + op->n =3D ((get_modrm(s, env) >> 3) & 7) | REX_R(s); + if (op->n >=3D 8) { + /* + * illegal opcode. The DR4 and DR5 case is checked in the gen= erated + * code instead, to save on hflags bits. + */ + return false; + } + if (decode->e.intercept) { + decode->e.intercept +=3D op->n; + } + break; =20 case X86_TYPE_G: /* REG in the modrm byte selects a GPR */ op->unit =3D X86_OP_INT; @@ -2431,7 +2487,6 @@ static void disas_insn(DisasContext *s, CPUState *cpu) case 0x00 ... 0x03: /* mostly privileged instructions */ case 0x05 ... 0x09: case 0x1a ... 0x1b: /* MPX */ - case 0x20 ... 0x23: /* mov from/to CR and DR */ case 0x30 ... 0x35: /* more privileged instructions */ case 0xa2 ... 0xa5: /* CPUID, BT, SHLD */ case 0xaa ... 0xae: /* RSM, SHRD, grp15 */ diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc index e6521632edd..db56bf7aee1 100644 --- a/target/i386/tcg/emit.c.inc +++ b/target/i386/tcg/emit.c.inc @@ -242,12 +242,20 @@ static void gen_load(DisasContext *s, X86DecodedInsn = *decode, int opn, TCGv v) tcg_gen_ld32u_tl(v, tcg_env, offsetof(CPUX86State,segs[op->n].selector)); break; +#ifndef CONFIG_USER_ONLY case X86_OP_CR: - tcg_gen_ld_tl(v, tcg_env, offsetof(CPUX86State, cr[op->n])); + if (op->n =3D=3D 8) { + translator_io_start(&s->base); + gen_helper_read_crN(v, tcg_env, tcg_constant_i32(op->n)); + } else { + tcg_gen_ld_tl(v, tcg_env, offsetof(CPUX86State, cr[op->n])); + } break; case X86_OP_DR: - tcg_gen_ld_tl(v, tcg_env, offsetof(CPUX86State, dr[op->n])); + /* CR4.DE tested in the helper. */ + gen_helper_get_dr(v, tcg_env, tcg_constant_i32(op->n)); break; +#endif case X86_OP_INT: if (op->has_ea) { if (v =3D=3D s->T0 && decode->e.special =3D=3D X86_SPECIAL_SEx= tT0) { @@ -343,8 +351,20 @@ static void gen_writeback(DisasContext *s, X86DecodedI= nsn *decode, int opn, TCGv 16, 16, 0); } break; +#ifndef CONFIG_USER_ONLY case X86_OP_CR: + if (op->n =3D=3D 8) { + translator_io_start(&s->base); + } + gen_helper_write_crN(tcg_env, tcg_constant_i32(op->n), v); + s->base.is_jmp =3D DISAS_EOB_NEXT; + break; case X86_OP_DR: + /* CR4.DE tested in the helper. */ + gen_helper_set_dr(tcg_env, tcg_constant_i32(op->n), v); + s->base.is_jmp =3D DISAS_EOB_NEXT; + break; +#endif default: g_assert_not_reached(); } --=20 2.45.2