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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f855e7ca78sm56258705ad.106.2024.06.15.19.47.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 15 Jun 2024 19:47:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1718506035; x=1719110835; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4Zx8it72Zy7Z5HxasQNNaxMP/T5FQJ8nmED3Hly6Uyg=; b=XYZSSuMOL6sATp2WoZJXkFMxMGBtdAC22y202yJ89KJn9z8UQjmY8G5DogEecK+tc4 ktfXB3l5uvFM+gicql6fqHrFtazYXBpPfZXkKg6oS/OHIfqypgvo70hd3WYRv8TtCP8Y 0nHkWKv0SVJuwuXcDk5DaAtBBDO4KWpdxPCdHZpDN/bLoN0gFZ7YE8m2Def+Uf+swIB/ in7WPCdh2uTfuhlZ01TYh/ZQxpk5UvTdfdgb4Tj8l5EKhaDIHZRDSGMCzckJ77Gs0ePd KOUl5GKcDCLwR/+FeBZEyfBsxP99B5POsC2qqbmNx4pWvfSE2rlyY03Pz+GnCQYlzGrC GxBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1718506035; x=1719110835; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4Zx8it72Zy7Z5HxasQNNaxMP/T5FQJ8nmED3Hly6Uyg=; b=IEBxXDB665SDlWuKZIKDZkLITCLf7WTt1wda2RSfWkDwZXbjYJ7Qbo0M8wEoYqU9a2 3j6W4okoRvhbRed7/Grnta+Mqmr30AV5B4KrtiGT4ccIiBzC0oURUPzRK/ygPegWswdf YJ6e2ORdMq6fKgOnZWKDRMf8YiqeYPuiFD8+v4zuQcz8X8nzoIrcyneDtQO0h3FTqgg9 Y5s0VMzKkWqTWwxVGoLr7r0mUsLheM9KNf7FTGw4tDnr9pSYuviR8EYVV6y8Pbw90NEy 1Wk/LP8828Suks2MF2/s9ltBn/i5nEcf97DUzgkXLvHSwQaknGgIwkpx4wFo5Rwsc8Ul a/fA== X-Gm-Message-State: AOJu0Yy/5qEbUj95/UZfUoPgHNuQBfOi/tNDATRPdY7unuGSSPP1kTKK ENVXh+SxW+0B9dQJXKgya6NKSohEG3xIDV+/pW/NQ5Td1/T7kdS410i9jtp5lD/Tnv/lsSqQl0o mWVGw8fj85mhGQIVi3136Zaf66UzA6Wu1fl5gxk3djVvcID4hos8tQBLTPKxMiwxUuRV4MIVJIt Sd9dXT+jOGt7FV/Jv8h8QROq1QYWHk3X+Dd9IM4ms= X-Google-Smtp-Source: AGHT+IGSv3zdtIKPscfm5xzHKxjYzELkUR0jj257FJoS+Z0FeFZOz7XLxnwYBdZv9j0OUtk8okqiSg== X-Received: by 2002:a17:902:7883:b0:1f6:1780:f7b1 with SMTP id d9443c01a7336-1f8625d3880mr55457285ad.17.1718506034491; Sat, 15 Jun 2024 19:47:14 -0700 (PDT) From: frank.chang@sifive.com To: qemu-devel@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , qemu-riscv@nongnu.org (open list:RISC-V TCG CPUs), Frank Chang , Jerry Zhang Jian , Max Chou Subject: [PATCH v2 4/6] target/riscv: Add standard extension implied rules Date: Sun, 16 Jun 2024 10:46:55 +0800 Message-ID: <20240616024657.17948-5-frank.chang@sifive.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240616024657.17948-1-frank.chang@sifive.com> References: <20240616024657.17948-1-frank.chang@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=frank.chang@sifive.com; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01, UPPERCASE_50_75=0.008 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1718506135428100005 Content-Type: text/plain; charset="utf-8" From: Frank Chang Add standard extension implied rules to enable the implied extensions of the standard extension recursively. Signed-off-by: Frank Chang Reviewed-by: Jerry Zhang Jian Tested-by: Max Chou Acked-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 340 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 340 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index d09b5e9e62..1a3b1387e1 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -2297,12 +2297,352 @@ static RISCVCPUImpliedExtsRule RVV_IMPLIED =3D { }, }; =20 +static RISCVCPUImpliedExtsRule ZCB_IMPLIED =3D { + .ext =3D CPU_CFG_OFFSET(ext_zcb), + .implied_exts =3D { + CPU_CFG_OFFSET(ext_zca), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + +static RISCVCPUImpliedExtsRule ZCD_IMPLIED =3D { + .ext =3D CPU_CFG_OFFSET(ext_zcd), + .implied_misas =3D RVD, + .implied_exts =3D { + CPU_CFG_OFFSET(ext_zca), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + +static RISCVCPUImpliedExtsRule ZCE_IMPLIED =3D { + .ext =3D CPU_CFG_OFFSET(ext_zce), + .implied_exts =3D { + CPU_CFG_OFFSET(ext_zcb), CPU_CFG_OFFSET(ext_zcmp), + CPU_CFG_OFFSET(ext_zcmt), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + +static RISCVCPUImpliedExtsRule ZCF_IMPLIED =3D { + .ext =3D CPU_CFG_OFFSET(ext_zcf), + .implied_misas =3D RVF, + .implied_exts =3D { + CPU_CFG_OFFSET(ext_zca), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + +static RISCVCPUImpliedExtsRule ZCMP_IMPLIED =3D { + .ext =3D CPU_CFG_OFFSET(ext_zcmp), + .implied_exts =3D { + CPU_CFG_OFFSET(ext_zca), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + +static RISCVCPUImpliedExtsRule ZCMT_IMPLIED =3D { + .ext =3D CPU_CFG_OFFSET(ext_zcmt), + .implied_exts =3D { + CPU_CFG_OFFSET(ext_zca), CPU_CFG_OFFSET(ext_zicsr), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + +static RISCVCPUImpliedExtsRule ZDINX_IMPLIED =3D { + .ext =3D CPU_CFG_OFFSET(ext_zdinx), + .implied_exts =3D { + CPU_CFG_OFFSET(ext_zfinx), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + +static RISCVCPUImpliedExtsRule ZFA_IMPLIED =3D { + .ext =3D CPU_CFG_OFFSET(ext_zfa), + .implied_misas =3D RVF, + .implied_exts =3D { RISCV_IMPLIED_EXTS_RULE_END }, +}; + +static RISCVCPUImpliedExtsRule ZFBFMIN_IMPLIED =3D { + .ext =3D CPU_CFG_OFFSET(ext_zfbfmin), + .implied_misas =3D RVF, + .implied_exts =3D { RISCV_IMPLIED_EXTS_RULE_END }, +}; + +static RISCVCPUImpliedExtsRule ZFH_IMPLIED =3D { + .ext =3D CPU_CFG_OFFSET(ext_zfh), + .implied_exts =3D { + CPU_CFG_OFFSET(ext_zfhmin), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + +static RISCVCPUImpliedExtsRule ZFHMIN_IMPLIED =3D { + .ext =3D CPU_CFG_OFFSET(ext_zfhmin), + .implied_misas =3D RVF, + .implied_exts =3D { RISCV_IMPLIED_EXTS_RULE_END }, +}; + +static RISCVCPUImpliedExtsRule ZFINX_IMPLIED =3D { + .ext =3D CPU_CFG_OFFSET(ext_zfinx), + .implied_exts =3D { + CPU_CFG_OFFSET(ext_zicsr), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + +static RISCVCPUImpliedExtsRule ZHINX_IMPLIED =3D { + .ext =3D CPU_CFG_OFFSET(ext_zhinx), + .implied_exts =3D { + CPU_CFG_OFFSET(ext_zhinxmin), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + +static RISCVCPUImpliedExtsRule ZHINXMIN_IMPLIED =3D { + .ext =3D CPU_CFG_OFFSET(ext_zhinxmin), + .implied_exts =3D { + CPU_CFG_OFFSET(ext_zfinx), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + +static RISCVCPUImpliedExtsRule ZICNTR_IMPLIED =3D { + .ext =3D CPU_CFG_OFFSET(ext_zicntr), + .implied_exts =3D { + CPU_CFG_OFFSET(ext_zicsr), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + +static RISCVCPUImpliedExtsRule ZIHPM_IMPLIED =3D { + .ext =3D CPU_CFG_OFFSET(ext_zihpm), + .implied_exts =3D { + CPU_CFG_OFFSET(ext_zicsr), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + +static RISCVCPUImpliedExtsRule ZK_IMPLIED =3D { + .ext =3D CPU_CFG_OFFSET(ext_zk), + .implied_exts =3D { + CPU_CFG_OFFSET(ext_zkn), CPU_CFG_OFFSET(ext_zkr), + CPU_CFG_OFFSET(ext_zkt), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + +static RISCVCPUImpliedExtsRule ZKN_IMPLIED =3D { + .ext =3D CPU_CFG_OFFSET(ext_zkn), + .implied_exts =3D { + CPU_CFG_OFFSET(ext_zbkb), CPU_CFG_OFFSET(ext_zbkc), + CPU_CFG_OFFSET(ext_zbkx), CPU_CFG_OFFSET(ext_zkne), + CPU_CFG_OFFSET(ext_zknd), CPU_CFG_OFFSET(ext_zknh), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + +static RISCVCPUImpliedExtsRule ZKS_IMPLIED =3D { + .ext =3D CPU_CFG_OFFSET(ext_zks), + .implied_exts =3D { + CPU_CFG_OFFSET(ext_zbkb), CPU_CFG_OFFSET(ext_zbkc), + CPU_CFG_OFFSET(ext_zbkx), CPU_CFG_OFFSET(ext_zksed), + CPU_CFG_OFFSET(ext_zksh), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + +static RISCVCPUImpliedExtsRule ZVBB_IMPLIED =3D { + .ext =3D CPU_CFG_OFFSET(ext_zvbb), + .implied_exts =3D { + CPU_CFG_OFFSET(ext_zvkb), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + +static RISCVCPUImpliedExtsRule ZVE32F_IMPLIED =3D { + .ext =3D CPU_CFG_OFFSET(ext_zve32f), + .implied_misas =3D RVF, + .implied_exts =3D { + CPU_CFG_OFFSET(ext_zve32x), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + +static RISCVCPUImpliedExtsRule ZVE32X_IMPLIED =3D { + .ext =3D CPU_CFG_OFFSET(ext_zve32x), + .implied_exts =3D { + CPU_CFG_OFFSET(ext_zicsr), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + +static RISCVCPUImpliedExtsRule ZVE64D_IMPLIED =3D { + .ext =3D CPU_CFG_OFFSET(ext_zve64d), + .implied_misas =3D RVD, + .implied_exts =3D { + CPU_CFG_OFFSET(ext_zve64f), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + +static RISCVCPUImpliedExtsRule ZVE64F_IMPLIED =3D { + .ext =3D CPU_CFG_OFFSET(ext_zve64f), + .implied_misas =3D RVF, + .implied_exts =3D { + CPU_CFG_OFFSET(ext_zve32f), CPU_CFG_OFFSET(ext_zve64x), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + +static RISCVCPUImpliedExtsRule ZVE64X_IMPLIED =3D { + .ext =3D CPU_CFG_OFFSET(ext_zve64x), + .implied_exts =3D { + CPU_CFG_OFFSET(ext_zve32x), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + +static RISCVCPUImpliedExtsRule ZVFBFMIN_IMPLIED =3D { + .ext =3D CPU_CFG_OFFSET(ext_zvfbfmin), + .implied_exts =3D { + CPU_CFG_OFFSET(ext_zve32f), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + +static RISCVCPUImpliedExtsRule ZVFBFWMA_IMPLIED =3D { + .ext =3D CPU_CFG_OFFSET(ext_zvfbfwma), + .implied_exts =3D { + CPU_CFG_OFFSET(ext_zvfbfmin), CPU_CFG_OFFSET(ext_zfbfmin), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + +static RISCVCPUImpliedExtsRule ZVFH_IMPLIED =3D { + .ext =3D CPU_CFG_OFFSET(ext_zvfh), + .implied_exts =3D { + CPU_CFG_OFFSET(ext_zvfhmin), CPU_CFG_OFFSET(ext_zfhmin), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + +static RISCVCPUImpliedExtsRule ZVFHMIN_IMPLIED =3D { + .ext =3D CPU_CFG_OFFSET(ext_zvfhmin), + .implied_exts =3D { + CPU_CFG_OFFSET(ext_zve32f), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + +static RISCVCPUImpliedExtsRule ZVKN_IMPLIED =3D { + .ext =3D CPU_CFG_OFFSET(ext_zvkn), + .implied_exts =3D { + CPU_CFG_OFFSET(ext_zvkned), CPU_CFG_OFFSET(ext_zvknhb), + CPU_CFG_OFFSET(ext_zvkb), CPU_CFG_OFFSET(ext_zvkt), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + +static RISCVCPUImpliedExtsRule ZVKNC_IMPLIED =3D { + .ext =3D CPU_CFG_OFFSET(ext_zvknc), + .implied_exts =3D { + CPU_CFG_OFFSET(ext_zvkn), CPU_CFG_OFFSET(ext_zvbc), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + +static RISCVCPUImpliedExtsRule ZVKNG_IMPLIED =3D { + .ext =3D CPU_CFG_OFFSET(ext_zvkng), + .implied_exts =3D { + CPU_CFG_OFFSET(ext_zvkn), CPU_CFG_OFFSET(ext_zvkg), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + +static RISCVCPUImpliedExtsRule ZVKNHB_IMPLIED =3D { + .ext =3D CPU_CFG_OFFSET(ext_zvknhb), + .implied_exts =3D { + CPU_CFG_OFFSET(ext_zve64x), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + +static RISCVCPUImpliedExtsRule ZVKS_IMPLIED =3D { + .ext =3D CPU_CFG_OFFSET(ext_zvks), + .implied_exts =3D { + CPU_CFG_OFFSET(ext_zvksed), CPU_CFG_OFFSET(ext_zvksh), + CPU_CFG_OFFSET(ext_zvkb), CPU_CFG_OFFSET(ext_zvkt), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + +static RISCVCPUImpliedExtsRule ZVKSC_IMPLIED =3D { + .ext =3D CPU_CFG_OFFSET(ext_zvksc), + .implied_exts =3D { + CPU_CFG_OFFSET(ext_zvks), CPU_CFG_OFFSET(ext_zvbc), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + +static RISCVCPUImpliedExtsRule ZVKSG_IMPLIED =3D { + .ext =3D CPU_CFG_OFFSET(ext_zvksg), + .implied_exts =3D { + CPU_CFG_OFFSET(ext_zvks), CPU_CFG_OFFSET(ext_zvkg), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + RISCVCPUImpliedExtsRule *riscv_misa_implied_rules[] =3D { &RVA_IMPLIED, &RVD_IMPLIED, &RVF_IMPLIED, &RVM_IMPLIED, &RVV_IMPLIED, NULL }; =20 RISCVCPUImpliedExtsRule *riscv_ext_implied_rules[] =3D { + &ZCB_IMPLIED, &ZCD_IMPLIED, &ZCE_IMPLIED, + &ZCF_IMPLIED, &ZCMP_IMPLIED, &ZCMT_IMPLIED, + &ZDINX_IMPLIED, &ZFA_IMPLIED, &ZFBFMIN_IMPLIED, + &ZFH_IMPLIED, &ZFHMIN_IMPLIED, &ZFINX_IMPLIED, + &ZHINX_IMPLIED, &ZHINXMIN_IMPLIED, &ZICNTR_IMPLIED, + &ZIHPM_IMPLIED, &ZK_IMPLIED, &ZKN_IMPLIED, + &ZKS_IMPLIED, &ZVBB_IMPLIED, &ZVE32F_IMPLIED, + &ZVE32X_IMPLIED, &ZVE64D_IMPLIED, &ZVE64F_IMPLIED, + &ZVE64X_IMPLIED, &ZVFBFMIN_IMPLIED, &ZVFBFWMA_IMPLIED, + &ZVFH_IMPLIED, &ZVFHMIN_IMPLIED, &ZVKN_IMPLIED, + &ZVKNC_IMPLIED, &ZVKNG_IMPLIED, &ZVKNHB_IMPLIED, + &ZVKS_IMPLIED, &ZVKSC_IMPLIED, &ZVKSG_IMPLIED, NULL }; =20 --=20 2.43.2