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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f855e7ca78sm56258705ad.106.2024.06.15.19.47.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 15 Jun 2024 19:47:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1718506032; x=1719110832; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wqwE76CQo0Svp3wf95GRe/VgtMvrGF7qfdx6aXlVV2E=; b=Efh1i7C4cSBV4MPDdzwdG56GvezwwzE/fSFBV7obh5FpY6ZfLs5VXyFYFmgYnTSAnE uBKXzoIE/2RUYMD4QbH/0/NWHzY9LbR6GhK6jQ+gkMEjwMlgHKIy8K9ImFEAV3NZap7k C2LgPApF0ww/szZ8oaFZMVLZNrtr9nawCTTJKn+DH3axCIkDrePERBd7fg2+hwrjcRE4 uoihCIV/wa/KwQTYyqfM6oNS6E8O+ki0AQPZ3fR717ZIZ8uFK6u9WOLdpyWIJsOLN4kl WbPyv0Y/xVAAH8byIWnoHRKV99IR2tIY+fkrjOCHths6vq709T389PI+NkSp2DEtiDji jldQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1718506032; x=1719110832; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wqwE76CQo0Svp3wf95GRe/VgtMvrGF7qfdx6aXlVV2E=; b=jIWebJV3v3MeW/+VRcTua5Brcn33h7VBX39uNJYSBgUbivLUQCUutdmRma59cjNl4u o5FUF3X68t6yl5sYShv9hg3uwIk+ll8hibuWJw9AVnIatXG5bwLxSlUx1jqw/uovI0t6 XqVrLPhPe92nCLts0rFplOR6O8AxrzHvhaPOUTWDqgzqCC6MPUC5kQU02n62epFX5A8L bkTmXyGCAE0dkS5XlgjLr/u/YtiWintM1pRKD3AqzmTDcYSngoJ9jYAhZ9w37G4Wn9CC oCzm6yzpgXwHK2TP6/eMmvBrPoapRQE2gYjDT9Ik1iUMR9GtQurFi5IXiTg1nl/RBoCL fptQ== X-Gm-Message-State: AOJu0YxvyvQTroDLTTiz9MVQ/3wItVPbbOJi6Ne4a3siheAdnp9Wjs13 Gg0i3yMWnXpc91RiTHAnFNB8os/L8aFnEG/RpPrbozJfbFs1+vnp7S6jy+D22GdkeKIt5fSUwqu 31gznay3g0nobQ6HqFn3xZw1GilL6d+LICHnQHEWpYKu9FxZ6l6N+5Kjpf5kuHWnx83qUY053P9 dF0Ae7/gntD41JTnNpRfWqMIlCnRjq+7nPRAdnayM= X-Google-Smtp-Source: AGHT+IHXX137WNtDA7G1jtTkWSmPNDhh34VM5ttJo/6kxH2m14azQysbNIxhtDWcM7atKf4QUe+ocg== X-Received: by 2002:a17:902:c94d:b0:1f7:1688:9e36 with SMTP id d9443c01a7336-1f86290073cmr72887745ad.48.1718506031945; Sat, 15 Jun 2024 19:47:11 -0700 (PDT) From: frank.chang@sifive.com To: qemu-devel@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , qemu-riscv@nongnu.org (open list:RISC-V TCG CPUs), Frank Chang , Jerry Zhang Jian , Max Chou Subject: [PATCH v2 3/6] target/riscv: Add MISA implied rules Date: Sun, 16 Jun 2024 10:46:54 +0800 Message-ID: <20240616024657.17948-4-frank.chang@sifive.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240616024657.17948-1-frank.chang@sifive.com> References: <20240616024657.17948-1-frank.chang@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=frank.chang@sifive.com; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1718506115346100011 Content-Type: text/plain; charset="utf-8" From: Frank Chang Add MISA extension implied rules to enable the implied extensions of MISA recursively. Signed-off-by: Frank Chang Reviewed-by: Jerry Zhang Jian Tested-by: Max Chou Reviewed-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 50 +++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 49 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index bacbb32120..d09b5e9e62 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -2250,8 +2250,56 @@ RISCVCPUProfile *riscv_profiles[] =3D { NULL, }; =20 +static RISCVCPUImpliedExtsRule RVA_IMPLIED =3D { + .is_misa =3D true, + .ext =3D RVA, + .implied_exts =3D { + CPU_CFG_OFFSET(ext_zalrsc), CPU_CFG_OFFSET(ext_zaamo), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + +static RISCVCPUImpliedExtsRule RVD_IMPLIED =3D { + .is_misa =3D true, + .ext =3D RVD, + .implied_misas =3D RVF, + .implied_exts =3D { RISCV_IMPLIED_EXTS_RULE_END }, +}; + +static RISCVCPUImpliedExtsRule RVF_IMPLIED =3D { + .is_misa =3D true, + .ext =3D RVF, + .implied_exts =3D { + CPU_CFG_OFFSET(ext_zicsr), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + +static RISCVCPUImpliedExtsRule RVM_IMPLIED =3D { + .is_misa =3D true, + .ext =3D RVM, + .implied_exts =3D { + CPU_CFG_OFFSET(ext_zmmul), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + +static RISCVCPUImpliedExtsRule RVV_IMPLIED =3D { + .is_misa =3D true, + .ext =3D RVV, + .implied_exts =3D { + CPU_CFG_OFFSET(ext_zve64d), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + RISCVCPUImpliedExtsRule *riscv_misa_implied_rules[] =3D { - NULL + &RVA_IMPLIED, &RVD_IMPLIED, &RVF_IMPLIED, + &RVM_IMPLIED, &RVV_IMPLIED, NULL }; =20 RISCVCPUImpliedExtsRule *riscv_ext_implied_rules[] =3D { --=20 2.43.2