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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f855e7ca78sm56258705ad.106.2024.06.15.19.47.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 15 Jun 2024 19:47:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1718506030; x=1719110830; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=LwRAet0mSxwn7I1Ml7pPtqRUk6TOfkcuiooaSBrc9bc=; b=TZIjMHr6gK/0X7VuaT7u6TjtPA+zWSTRV2QDToikjO8scBaDCuzpovmZ9GCGte5Fy/ zf91oWU2FSl6EDNVCKFtAM9vk89EfTc4Djl+FNDKNqkpOFkwoYH5FBJUjsUu1CO2ueSz k2t+M92x0zx32OX3LGxPxH5dYPnqYKzOLd67XOJppnWZuMQMhcAkJNxg1OLz3JYfgst1 g9TkGBqcaIQUzA2JLadQBuGIqShrWNprFZwqd4x4chquatXTSRFGHRXkDrI/Q4w6LRUE qYVf78Fdf0ULMQZg72tBi5zR4sHm9wjKyzEOpB3cuR1JRwvjJaG8ne3RP0ByUCs1BDG5 saGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1718506030; x=1719110830; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LwRAet0mSxwn7I1Ml7pPtqRUk6TOfkcuiooaSBrc9bc=; b=G6Y6NsfSuK2B9apw1MZ8/vW4LrIVKCAY82Vm6TcaLu1RXFEETJf+Y7wYf/wiRynHaL JpEkvK6WI2ZrEsHlUAvQ+DHhbFReKcTlemaVwxZXNhd4bwLiXmWDjbrT9/ZRFwSnr2ey M2ftxrJGE2tWM9tqkZfkk2pwJzTDKoBks6X/+uNJUw/M9/ZvdhTFtkuAPBQ7BM1/MPN5 ktvmN3s0/+BmSjczWj2Un8b68Rxb54nOMi3T6897ZRcs1Z/yfT2cVQ/YYvvhzzukH5jX UXAkJrpoc/RJ7xLUL7iBdUHbm6RsW8+xdWo/pwToFv27MQZWjKV3W6hLpK7usHwWnxaz 8aTA== X-Gm-Message-State: AOJu0YxaeVPpZIO+PGxuSUVuGaxjhGBZjDXC3iQyEn32NLIf6wFm0eid MZulIbnRkXFquqospabt0kJY1DK8eKx3gKWYdySe9Hf1Zr+VvmZbFgfw3wuHMpS0AHKzm9ztkY5 S/TD/5Qezw7YgnBlb93NTnVOBUrQHw1GJ5/eZL5EgfAgLWVqezUxS/tFQl/g+KyioYb8oBIg/cA ElOBwMu9JJK1Z8oX5A34+BCsNKhZJ4ye1gVLDUyFE= X-Google-Smtp-Source: AGHT+IF/vCFYU/v2WIebT7m51cTFH2hbWo7OVrqdOAnfFq9PZAwq4QPJZSYfDLjHHOQN2nrQdpVjBQ== X-Received: by 2002:a17:902:c943:b0:1f6:efd9:bec4 with SMTP id d9443c01a7336-1f8625cf93bmr87046655ad.19.1718506029564; Sat, 15 Jun 2024 19:47:09 -0700 (PDT) From: frank.chang@sifive.com To: qemu-devel@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , qemu-riscv@nongnu.org (open list:RISC-V TCG CPUs), Frank Chang , Jerry Zhang Jian , Max Chou Subject: [PATCH v2 2/6] target/riscv: Introduce extension implied rule helpers Date: Sun, 16 Jun 2024 10:46:53 +0800 Message-ID: <20240616024657.17948-3-frank.chang@sifive.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240616024657.17948-1-frank.chang@sifive.com> References: <20240616024657.17948-1-frank.chang@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=frank.chang@sifive.com; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1718506125385100003 Content-Type: text/plain; charset="utf-8" From: Frank Chang Introduce helpers to enable the extensions based on the implied rules. The implied extensions are enabled recursively, so we don't have to expand all of them manually. This also eliminates the old-fashioned ordering requirement. For example, Zvksg implies Zvks, Zvks implies Zvksed, etc., removing the need to check the implied rules of Zvksg before Zvks. Signed-off-by: Frank Chang Reviewed-by: Jerry Zhang Jian Tested-by: Max Chou Reviewed-by: Daniel Henrique Barboza --- target/riscv/tcg/tcg-cpu.c | 91 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 91 insertions(+) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index eb6f7b9d12..f8d6371764 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -36,6 +36,9 @@ static GHashTable *multi_ext_user_opts; static GHashTable *misa_ext_user_opts; =20 +static GHashTable *misa_implied_rules; +static GHashTable *ext_implied_rules; + static bool cpu_cfg_ext_is_user_set(uint32_t ext_offset) { return g_hash_table_contains(multi_ext_user_opts, @@ -836,11 +839,97 @@ static void riscv_cpu_validate_profiles(RISCVCPU *cpu) } } =20 +static void riscv_cpu_init_implied_exts_rules(void) +{ + RISCVCPUImpliedExtsRule *rule; + int i; + + for (i =3D 0; (rule =3D riscv_misa_implied_rules[i]); i++) { + g_hash_table_insert(misa_implied_rules, GUINT_TO_POINTER(rule->ext= ), + (gpointer)rule); + } + + for (i =3D 0; (rule =3D riscv_ext_implied_rules[i]); i++) { + g_hash_table_insert(ext_implied_rules, GUINT_TO_POINTER(rule->ext), + (gpointer)rule); + } +} + +static void cpu_enable_implied_rule(RISCVCPU *cpu, + RISCVCPUImpliedExtsRule *rule) +{ + CPURISCVState *env =3D &cpu->env; + RISCVCPUImpliedExtsRule *ir; + bool enabled =3D false; + int i; + +#ifndef CONFIG_USER_ONLY + enabled =3D qatomic_read(&rule->enabled) & BIT_ULL(cpu->env.mhartid); +#endif + + if (!enabled) { + /* Enable the implied MISAs. */ + if (rule->implied_misas) { + riscv_cpu_set_misa_ext(env, env->misa_ext | rule->implied_misa= s); + + for (i =3D 0; misa_bits[i] !=3D 0; i++) { + if (rule->implied_misas & misa_bits[i]) { + ir =3D g_hash_table_lookup(misa_implied_rules, + GUINT_TO_POINTER(misa_bits[i]= )); + + if (ir) { + cpu_enable_implied_rule(cpu, ir); + } + } + } + } + + /* Enable the implied extensions. */ + for (i =3D 0; rule->implied_exts[i] !=3D RISCV_IMPLIED_EXTS_RULE_E= ND; i++) { + cpu_cfg_ext_auto_update(cpu, rule->implied_exts[i], true); + + ir =3D g_hash_table_lookup(ext_implied_rules, + GUINT_TO_POINTER(rule->implied_exts[i= ])); + + if (ir) { + cpu_enable_implied_rule(cpu, ir); + } + } + +#ifndef CONFIG_USER_ONLY + qatomic_or(&rule->enabled, BIT_ULL(cpu->env.mhartid)); +#endif + } +} + +static void riscv_cpu_enable_implied_rules(RISCVCPU *cpu) +{ + RISCVCPUImpliedExtsRule *rule; + int i; + + /* Enable the implied MISAs. */ + for (i =3D 0; (rule =3D riscv_misa_implied_rules[i]); i++) { + if (riscv_has_ext(&cpu->env, rule->ext)) { + cpu_enable_implied_rule(cpu, rule); + } + } + + /* Enable the implied extensions. */ + for (i =3D 0; (rule =3D riscv_ext_implied_rules[i]); i++) { + if (isa_ext_is_enabled(cpu, rule->ext)) { + cpu_enable_implied_rule(cpu, rule); + } + } +} + void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp) { CPURISCVState *env =3D &cpu->env; Error *local_err =3D NULL; =20 + riscv_cpu_init_implied_exts_rules(); + riscv_cpu_enable_implied_rules(cpu); + riscv_cpu_validate_misa_priv(env, &local_err); if (local_err !=3D NULL) { error_propagate(errp, local_err); @@ -1346,6 +1435,8 @@ static void riscv_tcg_cpu_instance_init(CPUState *cs) =20 misa_ext_user_opts =3D g_hash_table_new(NULL, g_direct_equal); multi_ext_user_opts =3D g_hash_table_new(NULL, g_direct_equal); + misa_implied_rules =3D g_hash_table_new(NULL, g_direct_equal); + ext_implied_rules =3D g_hash_table_new(NULL, g_direct_equal); riscv_cpu_add_user_properties(obj); =20 if (riscv_cpu_has_max_extensions(obj)) { --=20 2.43.2