From nobody Mon Nov 25 04:41:26 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=sifive.com ARC-Seal: i=1; a=rsa-sha256; t=1718506134; cv=none; d=zohomail.com; s=zohoarc; b=PlGsx7bwY61CFJbwvY2AnSQqWG+JyagxiVwQnOtWrPHmoAexnycWKXESGiYEcvJq3YLLih6/EjcWjPRsqcWKNJvlTIEQK6/8hrVpNSPpFI+2ZCzPYaO9yShBwyO1XS590qEe1BwXBv3UiDJ9/zKlPXkt28Oc/jN4IRXdDRO/CJ8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1718506134; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=nQNMf+6wuwd34N5Qpr2xVvlJAXmEbxY00fEA9ntvmsU=; b=XanzTJl2oBnZhV8IA09+7qhKlqSFgKQgq6b4nxw51p/bCdLxn/a5vYwGiM3q5e2jd14l3lU8q9S9RXK0Fj1hTqlzoufikbhpRxdIAk6rnyOeflWE5HR2qxZPAyqk2RY4BrlWX3iz2XYtydfUha17ENqFZGe/szgwKk6OmMB7H2A= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1718506134905867.2546355799223; Sat, 15 Jun 2024 19:48:54 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sIfvM-0007R3-BH; Sat, 15 Jun 2024 22:47:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sIfvC-0007N7-QR for qemu-devel@nongnu.org; Sat, 15 Jun 2024 22:47:12 -0400 Received: from mail-io1-xd2c.google.com ([2607:f8b0:4864:20::d2c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sIfvB-0001h3-9E for qemu-devel@nongnu.org; Sat, 15 Jun 2024 22:47:10 -0400 Received: by mail-io1-xd2c.google.com with SMTP id ca18e2360f4ac-7e23dc4bda0so136488239f.3 for ; Sat, 15 Jun 2024 19:47:08 -0700 (PDT) Received: from hsinchu16.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f855e7ca78sm56258705ad.106.2024.06.15.19.47.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 15 Jun 2024 19:47:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1718506027; x=1719110827; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=nQNMf+6wuwd34N5Qpr2xVvlJAXmEbxY00fEA9ntvmsU=; b=Id6k+gNGqYDaXqUCcYCjdInyx2wD+ChSgT0ylo5NP32BOJg9CEQ+rodU5gax2SAkjX oufOUknvvbY+zfFwEZo6yke9dveKoVw/rM8c9LkY+kmgv/nS4W0C7lEliVBCDOGf/vza +8HMBalh7oZ1buS2UGGjEn70cyLWr5K7rRysC+WrgE8cqla/fZOHVlleI5VpUI/oLGpp BmC5ayRUxXitm5KIOXqxd47LPT0r7EPdUTElnD2k9lauthRebbMK7cAlkjOC8Ub0YFCW B9wBDvnVp+sipbGAMUP4Cp29RipWiL3kRvdS4T6JddLFzPrKV7fX2e0FXwoll9kVOP+V KGfQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1718506027; x=1719110827; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nQNMf+6wuwd34N5Qpr2xVvlJAXmEbxY00fEA9ntvmsU=; b=iEWkMGQ2be0hWfszgzdZ4wGjOxFSyfu7IB2AVx2RuMocaoNEOyJbGnKRhZev3d5pB6 LaNPHNn+ipolizaKbSwD/rtJZE669fnK3+Ob3EWBjQgfc95OdijHsimt0QBarzd3BFMz bnujUp88CqikAegCE8e8wbk8hsFzDnRK62+n3CyDeTmEuE1+NNYHkAnE7jzpZGekflJD k5VMt53t96g/aqkKlEmjIYYTwXtCNJGjgW+SMWVWdN8sL/CjaCIS3Oe1Awn4rjEvmjX1 uug6Kzow/eh+D3KeRvEd0/5Tz6TDN7XrHmHC8XNJAGOHHLgZI4OGNX90QLxqGQXXQdlC RZWQ== X-Gm-Message-State: AOJu0YwlS6ZXy8aPmjYU7v4O8IZvYaX3ID5ucv6oi7Ojw6aSH4HYNGkb T2pt4Vth7YGwTK86g9YxN+YiS3z0s13w/RkDMD6LCbaqErPW7Zuo74FygMSS6hTbX/QFdZm2FQZ t0adLDS0xUnmSG+Y1K5cAq+PVPVBxMW2st/nn5zw2hriNj9+E9f4w49XaM0GAKXxgvcj+bBpu8W g4U3SoU9xvG8pJ2WEl4ic48PpXml5GS1oZJ0j5iDE= X-Google-Smtp-Source: AGHT+IE0xIguhYHUiCnDxVpXM9r8oyIGirxsikhdNDjAwryUuR86cq1+ajvEmVL8nopuAmjKl/NKBw== X-Received: by 2002:a05:6602:1503:b0:7eb:78b4:faee with SMTP id ca18e2360f4ac-7ebeb4909cbmr763582639f.3.1718506027140; Sat, 15 Jun 2024 19:47:07 -0700 (PDT) From: frank.chang@sifive.com To: qemu-devel@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , qemu-riscv@nongnu.org (open list:RISC-V TCG CPUs), Frank Chang , Jerry Zhang Jian , Max Chou Subject: [PATCH v2 1/6] target/riscv: Introduce extension implied rules definition Date: Sun, 16 Jun 2024 10:46:52 +0800 Message-ID: <20240616024657.17948-2-frank.chang@sifive.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240616024657.17948-1-frank.chang@sifive.com> References: <20240616024657.17948-1-frank.chang@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::d2c; envelope-from=frank.chang@sifive.com; helo=mail-io1-xd2c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1718506135349100003 Content-Type: text/plain; charset="utf-8" From: Frank Chang RISCVCPUImpliedExtsRule is created to store the implied rules. 'is_misa' flag is used to distinguish whether the rule is derived from the MISA or other extensions. 'ext' stores the MISA bit if 'is_misa' is true. Otherwise, it stores the offset of the extension defined in RISCVCPUConfig. 'ext' will also serve as the key of the hash tables to look up the rule in the following commit. Signed-off-by: Frank Chang Reviewed-by: Jerry Zhang Jian Tested-by: Max Chou Reviewed-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 8 ++++++++ target/riscv/cpu.h | 25 +++++++++++++++++++++++++ 2 files changed, 33 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 4760cb2cc1..bacbb32120 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -2250,6 +2250,14 @@ RISCVCPUProfile *riscv_profiles[] =3D { NULL, }; =20 +RISCVCPUImpliedExtsRule *riscv_misa_implied_rules[] =3D { + NULL +}; + +RISCVCPUImpliedExtsRule *riscv_ext_implied_rules[] =3D { + NULL +}; + static Property riscv_cpu_properties[] =3D { DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), =20 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 90b8f1b08f..6b31731fa8 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -124,6 +124,31 @@ typedef enum { EXT_STATUS_DIRTY, } RISCVExtStatus; =20 +typedef struct riscv_cpu_implied_exts_rule RISCVCPUImpliedExtsRule; + +struct riscv_cpu_implied_exts_rule { +#ifndef CONFIG_USER_ONLY + /* + * Bitmask indicates the rule enabled status for the harts. + * This enhancement is only available in system-mode QEMU, + * as we don't have a good way (e.g. mhartid) to distinguish + * the SMP cores in user-mode QEMU. + */ + uint64_t enabled; +#endif + /* True if this is a MISA implied rule. */ + bool is_misa; + /* ext is MISA bit if is_misa flag is true, else extension offset. */ + const uint32_t ext; + const uint32_t implied_misas; + const uint32_t implied_exts[]; +}; + +extern RISCVCPUImpliedExtsRule *riscv_misa_implied_rules[]; +extern RISCVCPUImpliedExtsRule *riscv_ext_implied_rules[]; + +#define RISCV_IMPLIED_EXTS_RULE_END -1 + #define MMU_USER_IDX 3 =20 #define MAX_RISCV_PMPS (16) --=20 2.43.2