From nobody Mon Nov 25 01:37:50 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=sifive.com ARC-Seal: i=1; a=rsa-sha256; t=1718506134; cv=none; d=zohomail.com; s=zohoarc; b=PlGsx7bwY61CFJbwvY2AnSQqWG+JyagxiVwQnOtWrPHmoAexnycWKXESGiYEcvJq3YLLih6/EjcWjPRsqcWKNJvlTIEQK6/8hrVpNSPpFI+2ZCzPYaO9yShBwyO1XS590qEe1BwXBv3UiDJ9/zKlPXkt28Oc/jN4IRXdDRO/CJ8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1718506134; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=nQNMf+6wuwd34N5Qpr2xVvlJAXmEbxY00fEA9ntvmsU=; b=XanzTJl2oBnZhV8IA09+7qhKlqSFgKQgq6b4nxw51p/bCdLxn/a5vYwGiM3q5e2jd14l3lU8q9S9RXK0Fj1hTqlzoufikbhpRxdIAk6rnyOeflWE5HR2qxZPAyqk2RY4BrlWX3iz2XYtydfUha17ENqFZGe/szgwKk6OmMB7H2A= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1718506134905867.2546355799223; Sat, 15 Jun 2024 19:48:54 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sIfvM-0007R3-BH; Sat, 15 Jun 2024 22:47:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sIfvC-0007N7-QR for qemu-devel@nongnu.org; Sat, 15 Jun 2024 22:47:12 -0400 Received: from mail-io1-xd2c.google.com ([2607:f8b0:4864:20::d2c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sIfvB-0001h3-9E for qemu-devel@nongnu.org; Sat, 15 Jun 2024 22:47:10 -0400 Received: by mail-io1-xd2c.google.com with SMTP id ca18e2360f4ac-7e23dc4bda0so136488239f.3 for ; Sat, 15 Jun 2024 19:47:08 -0700 (PDT) Received: from hsinchu16.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f855e7ca78sm56258705ad.106.2024.06.15.19.47.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 15 Jun 2024 19:47:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1718506027; x=1719110827; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=nQNMf+6wuwd34N5Qpr2xVvlJAXmEbxY00fEA9ntvmsU=; b=Id6k+gNGqYDaXqUCcYCjdInyx2wD+ChSgT0ylo5NP32BOJg9CEQ+rodU5gax2SAkjX oufOUknvvbY+zfFwEZo6yke9dveKoVw/rM8c9LkY+kmgv/nS4W0C7lEliVBCDOGf/vza +8HMBalh7oZ1buS2UGGjEn70cyLWr5K7rRysC+WrgE8cqla/fZOHVlleI5VpUI/oLGpp BmC5ayRUxXitm5KIOXqxd47LPT0r7EPdUTElnD2k9lauthRebbMK7cAlkjOC8Ub0YFCW B9wBDvnVp+sipbGAMUP4Cp29RipWiL3kRvdS4T6JddLFzPrKV7fX2e0FXwoll9kVOP+V KGfQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1718506027; x=1719110827; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nQNMf+6wuwd34N5Qpr2xVvlJAXmEbxY00fEA9ntvmsU=; b=iEWkMGQ2be0hWfszgzdZ4wGjOxFSyfu7IB2AVx2RuMocaoNEOyJbGnKRhZev3d5pB6 LaNPHNn+ipolizaKbSwD/rtJZE669fnK3+Ob3EWBjQgfc95OdijHsimt0QBarzd3BFMz bnujUp88CqikAegCE8e8wbk8hsFzDnRK62+n3CyDeTmEuE1+NNYHkAnE7jzpZGekflJD k5VMt53t96g/aqkKlEmjIYYTwXtCNJGjgW+SMWVWdN8sL/CjaCIS3Oe1Awn4rjEvmjX1 uug6Kzow/eh+D3KeRvEd0/5Tz6TDN7XrHmHC8XNJAGOHHLgZI4OGNX90QLxqGQXXQdlC RZWQ== X-Gm-Message-State: AOJu0YwlS6ZXy8aPmjYU7v4O8IZvYaX3ID5ucv6oi7Ojw6aSH4HYNGkb T2pt4Vth7YGwTK86g9YxN+YiS3z0s13w/RkDMD6LCbaqErPW7Zuo74FygMSS6hTbX/QFdZm2FQZ t0adLDS0xUnmSG+Y1K5cAq+PVPVBxMW2st/nn5zw2hriNj9+E9f4w49XaM0GAKXxgvcj+bBpu8W g4U3SoU9xvG8pJ2WEl4ic48PpXml5GS1oZJ0j5iDE= X-Google-Smtp-Source: AGHT+IE0xIguhYHUiCnDxVpXM9r8oyIGirxsikhdNDjAwryUuR86cq1+ajvEmVL8nopuAmjKl/NKBw== X-Received: by 2002:a05:6602:1503:b0:7eb:78b4:faee with SMTP id ca18e2360f4ac-7ebeb4909cbmr763582639f.3.1718506027140; Sat, 15 Jun 2024 19:47:07 -0700 (PDT) From: frank.chang@sifive.com To: qemu-devel@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , qemu-riscv@nongnu.org (open list:RISC-V TCG CPUs), Frank Chang , Jerry Zhang Jian , Max Chou Subject: [PATCH v2 1/6] target/riscv: Introduce extension implied rules definition Date: Sun, 16 Jun 2024 10:46:52 +0800 Message-ID: <20240616024657.17948-2-frank.chang@sifive.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240616024657.17948-1-frank.chang@sifive.com> References: <20240616024657.17948-1-frank.chang@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::d2c; envelope-from=frank.chang@sifive.com; helo=mail-io1-xd2c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1718506135349100003 Content-Type: text/plain; charset="utf-8" From: Frank Chang RISCVCPUImpliedExtsRule is created to store the implied rules. 'is_misa' flag is used to distinguish whether the rule is derived from the MISA or other extensions. 'ext' stores the MISA bit if 'is_misa' is true. Otherwise, it stores the offset of the extension defined in RISCVCPUConfig. 'ext' will also serve as the key of the hash tables to look up the rule in the following commit. Signed-off-by: Frank Chang Reviewed-by: Jerry Zhang Jian Tested-by: Max Chou Reviewed-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 8 ++++++++ target/riscv/cpu.h | 25 +++++++++++++++++++++++++ 2 files changed, 33 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 4760cb2cc1..bacbb32120 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -2250,6 +2250,14 @@ RISCVCPUProfile *riscv_profiles[] =3D { NULL, }; =20 +RISCVCPUImpliedExtsRule *riscv_misa_implied_rules[] =3D { + NULL +}; + +RISCVCPUImpliedExtsRule *riscv_ext_implied_rules[] =3D { + NULL +}; + static Property riscv_cpu_properties[] =3D { DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), =20 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 90b8f1b08f..6b31731fa8 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -124,6 +124,31 @@ typedef enum { EXT_STATUS_DIRTY, } RISCVExtStatus; =20 +typedef struct riscv_cpu_implied_exts_rule RISCVCPUImpliedExtsRule; + +struct riscv_cpu_implied_exts_rule { +#ifndef CONFIG_USER_ONLY + /* + * Bitmask indicates the rule enabled status for the harts. + * This enhancement is only available in system-mode QEMU, + * as we don't have a good way (e.g. mhartid) to distinguish + * the SMP cores in user-mode QEMU. + */ + uint64_t enabled; +#endif + /* True if this is a MISA implied rule. */ + bool is_misa; + /* ext is MISA bit if is_misa flag is true, else extension offset. */ + const uint32_t ext; + const uint32_t implied_misas; + const uint32_t implied_exts[]; +}; + +extern RISCVCPUImpliedExtsRule *riscv_misa_implied_rules[]; +extern RISCVCPUImpliedExtsRule *riscv_ext_implied_rules[]; + +#define RISCV_IMPLIED_EXTS_RULE_END -1 + #define MMU_USER_IDX 3 =20 #define MAX_RISCV_PMPS (16) --=20 2.43.2 From nobody Mon Nov 25 01:37:50 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=sifive.com ARC-Seal: i=1; a=rsa-sha256; t=1718506123; cv=none; d=zohomail.com; s=zohoarc; b=PnyHJyTusEpFGz5g9k224t70T4XkaJ3D9DepSjjENTQvw0DrV3xTajuUjTiAvIP1OS1WwiiGl1MdSAtNfYZdBCtrPtv3gzXcuC8ECFqIrSTTp782pyJOZBC3UUZeUdGND0zGnlr5K8axekwxpRO03uvEIqEwStFb3siK5OpSAfQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1718506123; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=LwRAet0mSxwn7I1Ml7pPtqRUk6TOfkcuiooaSBrc9bc=; b=dPWSBzRdT2luEcjNBy4zUWjSPscxjM+9nFrGBPJS2PbhaVETjkStNWMa6j0t4Q+A57v2w4lJOcnysDohaVqdCsXRU6/1hHtYZr/nkNtCyatDZ9Jk7A06ZMmmu5UMBOPQiEKLwTtULasm2n0oBK4RJlpzHVi2F014lpeAUA+bKCY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1718506123832372.47075021714477; Sat, 15 Jun 2024 19:48:43 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sIfvK-0007P6-81; Sat, 15 Jun 2024 22:47:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sIfvF-0007NM-JM for qemu-devel@nongnu.org; Sat, 15 Jun 2024 22:47:17 -0400 Received: from mail-pl1-x634.google.com ([2607:f8b0:4864:20::634]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sIfvD-0001hW-UZ for qemu-devel@nongnu.org; Sat, 15 Jun 2024 22:47:13 -0400 Received: by mail-pl1-x634.google.com with SMTP id d9443c01a7336-1f480624d10so28588435ad.1 for ; Sat, 15 Jun 2024 19:47:11 -0700 (PDT) Received: from hsinchu16.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f855e7ca78sm56258705ad.106.2024.06.15.19.47.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 15 Jun 2024 19:47:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1718506030; x=1719110830; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=LwRAet0mSxwn7I1Ml7pPtqRUk6TOfkcuiooaSBrc9bc=; b=TZIjMHr6gK/0X7VuaT7u6TjtPA+zWSTRV2QDToikjO8scBaDCuzpovmZ9GCGte5Fy/ zf91oWU2FSl6EDNVCKFtAM9vk89EfTc4Djl+FNDKNqkpOFkwoYH5FBJUjsUu1CO2ueSz k2t+M92x0zx32OX3LGxPxH5dYPnqYKzOLd67XOJppnWZuMQMhcAkJNxg1OLz3JYfgst1 g9TkGBqcaIQUzA2JLadQBuGIqShrWNprFZwqd4x4chquatXTSRFGHRXkDrI/Q4w6LRUE qYVf78Fdf0ULMQZg72tBi5zR4sHm9wjKyzEOpB3cuR1JRwvjJaG8ne3RP0ByUCs1BDG5 saGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1718506030; x=1719110830; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LwRAet0mSxwn7I1Ml7pPtqRUk6TOfkcuiooaSBrc9bc=; b=G6Y6NsfSuK2B9apw1MZ8/vW4LrIVKCAY82Vm6TcaLu1RXFEETJf+Y7wYf/wiRynHaL JpEkvK6WI2ZrEsHlUAvQ+DHhbFReKcTlemaVwxZXNhd4bwLiXmWDjbrT9/ZRFwSnr2ey M2ftxrJGE2tWM9tqkZfkk2pwJzTDKoBks6X/+uNJUw/M9/ZvdhTFtkuAPBQ7BM1/MPN5 ktvmN3s0/+BmSjczWj2Un8b68Rxb54nOMi3T6897ZRcs1Z/yfT2cVQ/YYvvhzzukH5jX UXAkJrpoc/RJ7xLUL7iBdUHbm6RsW8+xdWo/pwToFv27MQZWjKV3W6hLpK7usHwWnxaz 8aTA== X-Gm-Message-State: AOJu0YxaeVPpZIO+PGxuSUVuGaxjhGBZjDXC3iQyEn32NLIf6wFm0eid MZulIbnRkXFquqospabt0kJY1DK8eKx3gKWYdySe9Hf1Zr+VvmZbFgfw3wuHMpS0AHKzm9ztkY5 S/TD/5Qezw7YgnBlb93NTnVOBUrQHw1GJ5/eZL5EgfAgLWVqezUxS/tFQl/g+KyioYb8oBIg/cA ElOBwMu9JJK1Z8oX5A34+BCsNKhZJ4ye1gVLDUyFE= X-Google-Smtp-Source: AGHT+IF/vCFYU/v2WIebT7m51cTFH2hbWo7OVrqdOAnfFq9PZAwq4QPJZSYfDLjHHOQN2nrQdpVjBQ== X-Received: by 2002:a17:902:c943:b0:1f6:efd9:bec4 with SMTP id d9443c01a7336-1f8625cf93bmr87046655ad.19.1718506029564; Sat, 15 Jun 2024 19:47:09 -0700 (PDT) From: frank.chang@sifive.com To: qemu-devel@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , qemu-riscv@nongnu.org (open list:RISC-V TCG CPUs), Frank Chang , Jerry Zhang Jian , Max Chou Subject: [PATCH v2 2/6] target/riscv: Introduce extension implied rule helpers Date: Sun, 16 Jun 2024 10:46:53 +0800 Message-ID: <20240616024657.17948-3-frank.chang@sifive.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240616024657.17948-1-frank.chang@sifive.com> References: <20240616024657.17948-1-frank.chang@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=frank.chang@sifive.com; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1718506125385100003 Content-Type: text/plain; charset="utf-8" From: Frank Chang Introduce helpers to enable the extensions based on the implied rules. The implied extensions are enabled recursively, so we don't have to expand all of them manually. This also eliminates the old-fashioned ordering requirement. For example, Zvksg implies Zvks, Zvks implies Zvksed, etc., removing the need to check the implied rules of Zvksg before Zvks. Signed-off-by: Frank Chang Reviewed-by: Jerry Zhang Jian Tested-by: Max Chou Reviewed-by: Daniel Henrique Barboza --- target/riscv/tcg/tcg-cpu.c | 91 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 91 insertions(+) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index eb6f7b9d12..f8d6371764 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -36,6 +36,9 @@ static GHashTable *multi_ext_user_opts; static GHashTable *misa_ext_user_opts; =20 +static GHashTable *misa_implied_rules; +static GHashTable *ext_implied_rules; + static bool cpu_cfg_ext_is_user_set(uint32_t ext_offset) { return g_hash_table_contains(multi_ext_user_opts, @@ -836,11 +839,97 @@ static void riscv_cpu_validate_profiles(RISCVCPU *cpu) } } =20 +static void riscv_cpu_init_implied_exts_rules(void) +{ + RISCVCPUImpliedExtsRule *rule; + int i; + + for (i =3D 0; (rule =3D riscv_misa_implied_rules[i]); i++) { + g_hash_table_insert(misa_implied_rules, GUINT_TO_POINTER(rule->ext= ), + (gpointer)rule); + } + + for (i =3D 0; (rule =3D riscv_ext_implied_rules[i]); i++) { + g_hash_table_insert(ext_implied_rules, GUINT_TO_POINTER(rule->ext), + (gpointer)rule); + } +} + +static void cpu_enable_implied_rule(RISCVCPU *cpu, + RISCVCPUImpliedExtsRule *rule) +{ + CPURISCVState *env =3D &cpu->env; + RISCVCPUImpliedExtsRule *ir; + bool enabled =3D false; + int i; + +#ifndef CONFIG_USER_ONLY + enabled =3D qatomic_read(&rule->enabled) & BIT_ULL(cpu->env.mhartid); +#endif + + if (!enabled) { + /* Enable the implied MISAs. */ + if (rule->implied_misas) { + riscv_cpu_set_misa_ext(env, env->misa_ext | rule->implied_misa= s); + + for (i =3D 0; misa_bits[i] !=3D 0; i++) { + if (rule->implied_misas & misa_bits[i]) { + ir =3D g_hash_table_lookup(misa_implied_rules, + GUINT_TO_POINTER(misa_bits[i]= )); + + if (ir) { + cpu_enable_implied_rule(cpu, ir); + } + } + } + } + + /* Enable the implied extensions. */ + for (i =3D 0; rule->implied_exts[i] !=3D RISCV_IMPLIED_EXTS_RULE_E= ND; i++) { + cpu_cfg_ext_auto_update(cpu, rule->implied_exts[i], true); + + ir =3D g_hash_table_lookup(ext_implied_rules, + GUINT_TO_POINTER(rule->implied_exts[i= ])); + + if (ir) { + cpu_enable_implied_rule(cpu, ir); + } + } + +#ifndef CONFIG_USER_ONLY + qatomic_or(&rule->enabled, BIT_ULL(cpu->env.mhartid)); +#endif + } +} + +static void riscv_cpu_enable_implied_rules(RISCVCPU *cpu) +{ + RISCVCPUImpliedExtsRule *rule; + int i; + + /* Enable the implied MISAs. */ + for (i =3D 0; (rule =3D riscv_misa_implied_rules[i]); i++) { + if (riscv_has_ext(&cpu->env, rule->ext)) { + cpu_enable_implied_rule(cpu, rule); + } + } + + /* Enable the implied extensions. */ + for (i =3D 0; (rule =3D riscv_ext_implied_rules[i]); i++) { + if (isa_ext_is_enabled(cpu, rule->ext)) { + cpu_enable_implied_rule(cpu, rule); + } + } +} + void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp) { CPURISCVState *env =3D &cpu->env; Error *local_err =3D NULL; =20 + riscv_cpu_init_implied_exts_rules(); + riscv_cpu_enable_implied_rules(cpu); + riscv_cpu_validate_misa_priv(env, &local_err); if (local_err !=3D NULL) { error_propagate(errp, local_err); @@ -1346,6 +1435,8 @@ static void riscv_tcg_cpu_instance_init(CPUState *cs) =20 misa_ext_user_opts =3D g_hash_table_new(NULL, g_direct_equal); multi_ext_user_opts =3D g_hash_table_new(NULL, g_direct_equal); + misa_implied_rules =3D g_hash_table_new(NULL, g_direct_equal); + ext_implied_rules =3D g_hash_table_new(NULL, g_direct_equal); riscv_cpu_add_user_properties(obj); =20 if (riscv_cpu_has_max_extensions(obj)) { --=20 2.43.2 From nobody Mon Nov 25 01:37:50 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=sifive.com ARC-Seal: i=1; a=rsa-sha256; t=1718506114; cv=none; d=zohomail.com; s=zohoarc; b=TJdjt9aKuBo5TJQK8ywKWjYx3cAY4mMiJS2Q5346FxufPnZgCGV62TbiWUjGpIgbqEu0/LC1A5QyERyDOYW8uAEp2SGipYsYNDZRX1qm55ZwSoTSOLrzSdTzge48J9MMYxuigeIcqL7DDY4/RhGaaTeb/DqpsSHdHRo0hMEAXRg= ARC-Message-Signature: i=1; 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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f855e7ca78sm56258705ad.106.2024.06.15.19.47.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 15 Jun 2024 19:47:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1718506032; x=1719110832; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wqwE76CQo0Svp3wf95GRe/VgtMvrGF7qfdx6aXlVV2E=; b=Efh1i7C4cSBV4MPDdzwdG56GvezwwzE/fSFBV7obh5FpY6ZfLs5VXyFYFmgYnTSAnE uBKXzoIE/2RUYMD4QbH/0/NWHzY9LbR6GhK6jQ+gkMEjwMlgHKIy8K9ImFEAV3NZap7k C2LgPApF0ww/szZ8oaFZMVLZNrtr9nawCTTJKn+DH3axCIkDrePERBd7fg2+hwrjcRE4 uoihCIV/wa/KwQTYyqfM6oNS6E8O+ki0AQPZ3fR717ZIZ8uFK6u9WOLdpyWIJsOLN4kl WbPyv0Y/xVAAH8byIWnoHRKV99IR2tIY+fkrjOCHths6vq709T389PI+NkSp2DEtiDji jldQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1718506032; x=1719110832; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wqwE76CQo0Svp3wf95GRe/VgtMvrGF7qfdx6aXlVV2E=; b=jIWebJV3v3MeW/+VRcTua5Brcn33h7VBX39uNJYSBgUbivLUQCUutdmRma59cjNl4u o5FUF3X68t6yl5sYShv9hg3uwIk+ll8hibuWJw9AVnIatXG5bwLxSlUx1jqw/uovI0t6 XqVrLPhPe92nCLts0rFplOR6O8AxrzHvhaPOUTWDqgzqCC6MPUC5kQU02n62epFX5A8L bkTmXyGCAE0dkS5XlgjLr/u/YtiWintM1pRKD3AqzmTDcYSngoJ9jYAhZ9w37G4Wn9CC oCzm6yzpgXwHK2TP6/eMmvBrPoapRQE2gYjDT9Ik1iUMR9GtQurFi5IXiTg1nl/RBoCL fptQ== X-Gm-Message-State: AOJu0YxvyvQTroDLTTiz9MVQ/3wItVPbbOJi6Ne4a3siheAdnp9Wjs13 Gg0i3yMWnXpc91RiTHAnFNB8os/L8aFnEG/RpPrbozJfbFs1+vnp7S6jy+D22GdkeKIt5fSUwqu 31gznay3g0nobQ6HqFn3xZw1GilL6d+LICHnQHEWpYKu9FxZ6l6N+5Kjpf5kuHWnx83qUY053P9 dF0Ae7/gntD41JTnNpRfWqMIlCnRjq+7nPRAdnayM= X-Google-Smtp-Source: AGHT+IHXX137WNtDA7G1jtTkWSmPNDhh34VM5ttJo/6kxH2m14azQysbNIxhtDWcM7atKf4QUe+ocg== X-Received: by 2002:a17:902:c94d:b0:1f7:1688:9e36 with SMTP id d9443c01a7336-1f86290073cmr72887745ad.48.1718506031945; Sat, 15 Jun 2024 19:47:11 -0700 (PDT) From: frank.chang@sifive.com To: qemu-devel@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , qemu-riscv@nongnu.org (open list:RISC-V TCG CPUs), Frank Chang , Jerry Zhang Jian , Max Chou Subject: [PATCH v2 3/6] target/riscv: Add MISA implied rules Date: Sun, 16 Jun 2024 10:46:54 +0800 Message-ID: <20240616024657.17948-4-frank.chang@sifive.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240616024657.17948-1-frank.chang@sifive.com> References: <20240616024657.17948-1-frank.chang@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=frank.chang@sifive.com; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1718506115346100011 Content-Type: text/plain; charset="utf-8" From: Frank Chang Add MISA extension implied rules to enable the implied extensions of MISA recursively. Signed-off-by: Frank Chang Reviewed-by: Jerry Zhang Jian Tested-by: Max Chou Reviewed-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 50 +++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 49 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index bacbb32120..d09b5e9e62 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -2250,8 +2250,56 @@ RISCVCPUProfile *riscv_profiles[] =3D { NULL, }; =20 +static RISCVCPUImpliedExtsRule RVA_IMPLIED =3D { + .is_misa =3D true, + .ext =3D RVA, + .implied_exts =3D { + CPU_CFG_OFFSET(ext_zalrsc), CPU_CFG_OFFSET(ext_zaamo), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + +static RISCVCPUImpliedExtsRule RVD_IMPLIED =3D { + .is_misa =3D true, + .ext =3D RVD, + .implied_misas =3D RVF, + .implied_exts =3D { RISCV_IMPLIED_EXTS_RULE_END }, +}; + +static RISCVCPUImpliedExtsRule RVF_IMPLIED =3D { + .is_misa =3D true, + .ext =3D RVF, + .implied_exts =3D { + CPU_CFG_OFFSET(ext_zicsr), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + +static RISCVCPUImpliedExtsRule RVM_IMPLIED =3D { + .is_misa =3D true, + .ext =3D RVM, + .implied_exts =3D { + CPU_CFG_OFFSET(ext_zmmul), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + +static RISCVCPUImpliedExtsRule RVV_IMPLIED =3D { + .is_misa =3D true, + .ext =3D RVV, + .implied_exts =3D { + CPU_CFG_OFFSET(ext_zve64d), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + RISCVCPUImpliedExtsRule *riscv_misa_implied_rules[] =3D { - NULL + &RVA_IMPLIED, &RVD_IMPLIED, &RVF_IMPLIED, + &RVM_IMPLIED, &RVV_IMPLIED, NULL }; =20 RISCVCPUImpliedExtsRule *riscv_ext_implied_rules[] =3D { --=20 2.43.2 From nobody Mon Nov 25 01:37:50 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=sifive.com ARC-Seal: i=1; a=rsa-sha256; t=1718506134; cv=none; d=zohomail.com; s=zohoarc; b=j8memmwNNWw4JG9Pe93eJEzr2mf8xrJEOPZIzXEmM2drhptRiI4oOeOhYE1Z5AgNQYybjaGu/MQelu11xaFH4yfE2KPdjTxYE2DQWGxIBGr32Hqf157d7dmYzioNNqTCaR7Gi+bL6zdF7j30s2UUrGsNeQjw69Sx0B60n/JUp10= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1718506134; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=4Zx8it72Zy7Z5HxasQNNaxMP/T5FQJ8nmED3Hly6Uyg=; b=PGBVtnfFlrIGMEPOG9H4wEcLb+XKtaWC2WHpb7f3qmgm+tHN0/5uLWUv1Cyi/Cnt85dFvAwZ3K2zTF+kfQhD7yHL2mP2n1K+ErlERbX2ABjFPryq/UB5SIha2+HqFgvLiGoabIDeL3/ptr44H/abegL2u/E13eHkzHCkkh8V/ng= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1718506134332920.9565613064617; Sat, 15 Jun 2024 19:48:54 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sIfvM-0007Re-Ug; Sat, 15 Jun 2024 22:47:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sIfvL-0007Pm-B5 for qemu-devel@nongnu.org; Sat, 15 Jun 2024 22:47:19 -0400 Received: from mail-pl1-x635.google.com ([2607:f8b0:4864:20::635]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sIfvJ-0001iG-BP for qemu-devel@nongnu.org; Sat, 15 Jun 2024 22:47:19 -0400 Received: by mail-pl1-x635.google.com with SMTP id d9443c01a7336-1f6da06ba24so29456895ad.2 for ; Sat, 15 Jun 2024 19:47:16 -0700 (PDT) Received: from hsinchu16.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f855e7ca78sm56258705ad.106.2024.06.15.19.47.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 15 Jun 2024 19:47:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1718506035; x=1719110835; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4Zx8it72Zy7Z5HxasQNNaxMP/T5FQJ8nmED3Hly6Uyg=; b=XYZSSuMOL6sATp2WoZJXkFMxMGBtdAC22y202yJ89KJn9z8UQjmY8G5DogEecK+tc4 ktfXB3l5uvFM+gicql6fqHrFtazYXBpPfZXkKg6oS/OHIfqypgvo70hd3WYRv8TtCP8Y 0nHkWKv0SVJuwuXcDk5DaAtBBDO4KWpdxPCdHZpDN/bLoN0gFZ7YE8m2Def+Uf+swIB/ in7WPCdh2uTfuhlZ01TYh/ZQxpk5UvTdfdgb4Tj8l5EKhaDIHZRDSGMCzckJ77Gs0ePd KOUl5GKcDCLwR/+FeBZEyfBsxP99B5POsC2qqbmNx4pWvfSE2rlyY03Pz+GnCQYlzGrC GxBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1718506035; x=1719110835; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4Zx8it72Zy7Z5HxasQNNaxMP/T5FQJ8nmED3Hly6Uyg=; b=IEBxXDB665SDlWuKZIKDZkLITCLf7WTt1wda2RSfWkDwZXbjYJ7Qbo0M8wEoYqU9a2 3j6W4okoRvhbRed7/Grnta+Mqmr30AV5B4KrtiGT4ccIiBzC0oURUPzRK/ygPegWswdf YJ6e2ORdMq6fKgOnZWKDRMf8YiqeYPuiFD8+v4zuQcz8X8nzoIrcyneDtQO0h3FTqgg9 Y5s0VMzKkWqTWwxVGoLr7r0mUsLheM9KNf7FTGw4tDnr9pSYuviR8EYVV6y8Pbw90NEy 1Wk/LP8828Suks2MF2/s9ltBn/i5nEcf97DUzgkXLvHSwQaknGgIwkpx4wFo5Rwsc8Ul a/fA== X-Gm-Message-State: AOJu0Yy/5qEbUj95/UZfUoPgHNuQBfOi/tNDATRPdY7unuGSSPP1kTKK ENVXh+SxW+0B9dQJXKgya6NKSohEG3xIDV+/pW/NQ5Td1/T7kdS410i9jtp5lD/Tnv/lsSqQl0o mWVGw8fj85mhGQIVi3136Zaf66UzA6Wu1fl5gxk3djVvcID4hos8tQBLTPKxMiwxUuRV4MIVJIt Sd9dXT+jOGt7FV/Jv8h8QROq1QYWHk3X+Dd9IM4ms= X-Google-Smtp-Source: AGHT+IGSv3zdtIKPscfm5xzHKxjYzELkUR0jj257FJoS+Z0FeFZOz7XLxnwYBdZv9j0OUtk8okqiSg== X-Received: by 2002:a17:902:7883:b0:1f6:1780:f7b1 with SMTP id d9443c01a7336-1f8625d3880mr55457285ad.17.1718506034491; Sat, 15 Jun 2024 19:47:14 -0700 (PDT) From: frank.chang@sifive.com To: qemu-devel@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , qemu-riscv@nongnu.org (open list:RISC-V TCG CPUs), Frank Chang , Jerry Zhang Jian , Max Chou Subject: [PATCH v2 4/6] target/riscv: Add standard extension implied rules Date: Sun, 16 Jun 2024 10:46:55 +0800 Message-ID: <20240616024657.17948-5-frank.chang@sifive.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240616024657.17948-1-frank.chang@sifive.com> References: <20240616024657.17948-1-frank.chang@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=frank.chang@sifive.com; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01, UPPERCASE_50_75=0.008 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1718506135428100005 Content-Type: text/plain; charset="utf-8" From: Frank Chang Add standard extension implied rules to enable the implied extensions of the standard extension recursively. Signed-off-by: Frank Chang Reviewed-by: Jerry Zhang Jian Tested-by: Max Chou Acked-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 340 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 340 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index d09b5e9e62..1a3b1387e1 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -2297,12 +2297,352 @@ static RISCVCPUImpliedExtsRule RVV_IMPLIED =3D { }, }; =20 +static RISCVCPUImpliedExtsRule ZCB_IMPLIED =3D { + .ext =3D CPU_CFG_OFFSET(ext_zcb), + .implied_exts =3D { + CPU_CFG_OFFSET(ext_zca), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + +static RISCVCPUImpliedExtsRule ZCD_IMPLIED =3D { + .ext =3D CPU_CFG_OFFSET(ext_zcd), + .implied_misas =3D RVD, + .implied_exts =3D { + CPU_CFG_OFFSET(ext_zca), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + +static RISCVCPUImpliedExtsRule ZCE_IMPLIED =3D { + .ext =3D CPU_CFG_OFFSET(ext_zce), + .implied_exts =3D { + CPU_CFG_OFFSET(ext_zcb), CPU_CFG_OFFSET(ext_zcmp), + CPU_CFG_OFFSET(ext_zcmt), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + +static RISCVCPUImpliedExtsRule ZCF_IMPLIED =3D { + .ext =3D CPU_CFG_OFFSET(ext_zcf), + .implied_misas =3D RVF, + .implied_exts =3D { + CPU_CFG_OFFSET(ext_zca), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + +static RISCVCPUImpliedExtsRule ZCMP_IMPLIED =3D { + .ext =3D CPU_CFG_OFFSET(ext_zcmp), + .implied_exts =3D { + CPU_CFG_OFFSET(ext_zca), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + +static RISCVCPUImpliedExtsRule ZCMT_IMPLIED =3D { + .ext =3D CPU_CFG_OFFSET(ext_zcmt), + .implied_exts =3D { + CPU_CFG_OFFSET(ext_zca), CPU_CFG_OFFSET(ext_zicsr), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + +static RISCVCPUImpliedExtsRule ZDINX_IMPLIED =3D { + .ext =3D CPU_CFG_OFFSET(ext_zdinx), + .implied_exts =3D { + CPU_CFG_OFFSET(ext_zfinx), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + +static RISCVCPUImpliedExtsRule ZFA_IMPLIED =3D { + .ext =3D CPU_CFG_OFFSET(ext_zfa), + .implied_misas =3D RVF, + .implied_exts =3D { RISCV_IMPLIED_EXTS_RULE_END }, +}; + +static RISCVCPUImpliedExtsRule ZFBFMIN_IMPLIED =3D { + .ext =3D CPU_CFG_OFFSET(ext_zfbfmin), + .implied_misas =3D RVF, + .implied_exts =3D { RISCV_IMPLIED_EXTS_RULE_END }, +}; + +static RISCVCPUImpliedExtsRule ZFH_IMPLIED =3D { + .ext =3D CPU_CFG_OFFSET(ext_zfh), + .implied_exts =3D { + CPU_CFG_OFFSET(ext_zfhmin), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + +static RISCVCPUImpliedExtsRule ZFHMIN_IMPLIED =3D { + .ext =3D CPU_CFG_OFFSET(ext_zfhmin), + .implied_misas =3D RVF, + .implied_exts =3D { RISCV_IMPLIED_EXTS_RULE_END }, +}; + +static RISCVCPUImpliedExtsRule ZFINX_IMPLIED =3D { + .ext =3D CPU_CFG_OFFSET(ext_zfinx), + .implied_exts =3D { + CPU_CFG_OFFSET(ext_zicsr), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + +static RISCVCPUImpliedExtsRule ZHINX_IMPLIED =3D { + .ext =3D CPU_CFG_OFFSET(ext_zhinx), + .implied_exts =3D { + CPU_CFG_OFFSET(ext_zhinxmin), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + +static RISCVCPUImpliedExtsRule ZHINXMIN_IMPLIED =3D { + .ext =3D CPU_CFG_OFFSET(ext_zhinxmin), + .implied_exts =3D { + CPU_CFG_OFFSET(ext_zfinx), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + +static RISCVCPUImpliedExtsRule ZICNTR_IMPLIED =3D { + .ext =3D CPU_CFG_OFFSET(ext_zicntr), + .implied_exts =3D { + CPU_CFG_OFFSET(ext_zicsr), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + +static RISCVCPUImpliedExtsRule ZIHPM_IMPLIED =3D { + .ext =3D CPU_CFG_OFFSET(ext_zihpm), + .implied_exts =3D { + CPU_CFG_OFFSET(ext_zicsr), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + +static RISCVCPUImpliedExtsRule ZK_IMPLIED =3D { + .ext =3D CPU_CFG_OFFSET(ext_zk), + .implied_exts =3D { + CPU_CFG_OFFSET(ext_zkn), CPU_CFG_OFFSET(ext_zkr), + CPU_CFG_OFFSET(ext_zkt), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + +static RISCVCPUImpliedExtsRule ZKN_IMPLIED =3D { + .ext =3D CPU_CFG_OFFSET(ext_zkn), + .implied_exts =3D { + CPU_CFG_OFFSET(ext_zbkb), CPU_CFG_OFFSET(ext_zbkc), + CPU_CFG_OFFSET(ext_zbkx), CPU_CFG_OFFSET(ext_zkne), + CPU_CFG_OFFSET(ext_zknd), CPU_CFG_OFFSET(ext_zknh), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + +static RISCVCPUImpliedExtsRule ZKS_IMPLIED =3D { + .ext =3D CPU_CFG_OFFSET(ext_zks), + .implied_exts =3D { + CPU_CFG_OFFSET(ext_zbkb), CPU_CFG_OFFSET(ext_zbkc), + CPU_CFG_OFFSET(ext_zbkx), CPU_CFG_OFFSET(ext_zksed), + CPU_CFG_OFFSET(ext_zksh), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + +static RISCVCPUImpliedExtsRule ZVBB_IMPLIED =3D { + .ext =3D CPU_CFG_OFFSET(ext_zvbb), + .implied_exts =3D { + CPU_CFG_OFFSET(ext_zvkb), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + +static RISCVCPUImpliedExtsRule ZVE32F_IMPLIED =3D { + .ext =3D CPU_CFG_OFFSET(ext_zve32f), + .implied_misas =3D RVF, + .implied_exts =3D { + CPU_CFG_OFFSET(ext_zve32x), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + +static RISCVCPUImpliedExtsRule ZVE32X_IMPLIED =3D { + .ext =3D CPU_CFG_OFFSET(ext_zve32x), + .implied_exts =3D { + CPU_CFG_OFFSET(ext_zicsr), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + +static RISCVCPUImpliedExtsRule ZVE64D_IMPLIED =3D { + .ext =3D CPU_CFG_OFFSET(ext_zve64d), + .implied_misas =3D RVD, + .implied_exts =3D { + CPU_CFG_OFFSET(ext_zve64f), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + +static RISCVCPUImpliedExtsRule ZVE64F_IMPLIED =3D { + .ext =3D CPU_CFG_OFFSET(ext_zve64f), + .implied_misas =3D RVF, + .implied_exts =3D { + CPU_CFG_OFFSET(ext_zve32f), CPU_CFG_OFFSET(ext_zve64x), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + +static RISCVCPUImpliedExtsRule ZVE64X_IMPLIED =3D { + .ext =3D CPU_CFG_OFFSET(ext_zve64x), + .implied_exts =3D { + CPU_CFG_OFFSET(ext_zve32x), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + +static RISCVCPUImpliedExtsRule ZVFBFMIN_IMPLIED =3D { + .ext =3D CPU_CFG_OFFSET(ext_zvfbfmin), + .implied_exts =3D { + CPU_CFG_OFFSET(ext_zve32f), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + +static RISCVCPUImpliedExtsRule ZVFBFWMA_IMPLIED =3D { + .ext =3D CPU_CFG_OFFSET(ext_zvfbfwma), + .implied_exts =3D { + CPU_CFG_OFFSET(ext_zvfbfmin), CPU_CFG_OFFSET(ext_zfbfmin), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + +static RISCVCPUImpliedExtsRule ZVFH_IMPLIED =3D { + .ext =3D CPU_CFG_OFFSET(ext_zvfh), + .implied_exts =3D { + CPU_CFG_OFFSET(ext_zvfhmin), CPU_CFG_OFFSET(ext_zfhmin), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + +static RISCVCPUImpliedExtsRule ZVFHMIN_IMPLIED =3D { + .ext =3D CPU_CFG_OFFSET(ext_zvfhmin), + .implied_exts =3D { + CPU_CFG_OFFSET(ext_zve32f), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + +static RISCVCPUImpliedExtsRule ZVKN_IMPLIED =3D { + .ext =3D CPU_CFG_OFFSET(ext_zvkn), + .implied_exts =3D { + CPU_CFG_OFFSET(ext_zvkned), CPU_CFG_OFFSET(ext_zvknhb), + CPU_CFG_OFFSET(ext_zvkb), CPU_CFG_OFFSET(ext_zvkt), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + +static RISCVCPUImpliedExtsRule ZVKNC_IMPLIED =3D { + .ext =3D CPU_CFG_OFFSET(ext_zvknc), + .implied_exts =3D { + CPU_CFG_OFFSET(ext_zvkn), CPU_CFG_OFFSET(ext_zvbc), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + +static RISCVCPUImpliedExtsRule ZVKNG_IMPLIED =3D { + .ext =3D CPU_CFG_OFFSET(ext_zvkng), + .implied_exts =3D { + CPU_CFG_OFFSET(ext_zvkn), CPU_CFG_OFFSET(ext_zvkg), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + +static RISCVCPUImpliedExtsRule ZVKNHB_IMPLIED =3D { + .ext =3D CPU_CFG_OFFSET(ext_zvknhb), + .implied_exts =3D { + CPU_CFG_OFFSET(ext_zve64x), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + +static RISCVCPUImpliedExtsRule ZVKS_IMPLIED =3D { + .ext =3D CPU_CFG_OFFSET(ext_zvks), + .implied_exts =3D { + CPU_CFG_OFFSET(ext_zvksed), CPU_CFG_OFFSET(ext_zvksh), + CPU_CFG_OFFSET(ext_zvkb), CPU_CFG_OFFSET(ext_zvkt), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + +static RISCVCPUImpliedExtsRule ZVKSC_IMPLIED =3D { + .ext =3D CPU_CFG_OFFSET(ext_zvksc), + .implied_exts =3D { + CPU_CFG_OFFSET(ext_zvks), CPU_CFG_OFFSET(ext_zvbc), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + +static RISCVCPUImpliedExtsRule ZVKSG_IMPLIED =3D { + .ext =3D CPU_CFG_OFFSET(ext_zvksg), + .implied_exts =3D { + CPU_CFG_OFFSET(ext_zvks), CPU_CFG_OFFSET(ext_zvkg), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + RISCVCPUImpliedExtsRule *riscv_misa_implied_rules[] =3D { &RVA_IMPLIED, &RVD_IMPLIED, &RVF_IMPLIED, &RVM_IMPLIED, &RVV_IMPLIED, NULL }; =20 RISCVCPUImpliedExtsRule *riscv_ext_implied_rules[] =3D { + &ZCB_IMPLIED, &ZCD_IMPLIED, &ZCE_IMPLIED, + &ZCF_IMPLIED, &ZCMP_IMPLIED, &ZCMT_IMPLIED, + &ZDINX_IMPLIED, &ZFA_IMPLIED, &ZFBFMIN_IMPLIED, + &ZFH_IMPLIED, &ZFHMIN_IMPLIED, &ZFINX_IMPLIED, + &ZHINX_IMPLIED, &ZHINXMIN_IMPLIED, &ZICNTR_IMPLIED, + &ZIHPM_IMPLIED, &ZK_IMPLIED, &ZKN_IMPLIED, + &ZKS_IMPLIED, &ZVBB_IMPLIED, &ZVE32F_IMPLIED, + &ZVE32X_IMPLIED, &ZVE64D_IMPLIED, &ZVE64F_IMPLIED, + &ZVE64X_IMPLIED, &ZVFBFMIN_IMPLIED, &ZVFBFWMA_IMPLIED, + &ZVFH_IMPLIED, &ZVFHMIN_IMPLIED, &ZVKN_IMPLIED, + &ZVKNC_IMPLIED, &ZVKNG_IMPLIED, &ZVKNHB_IMPLIED, + &ZVKS_IMPLIED, &ZVKSC_IMPLIED, &ZVKSG_IMPLIED, NULL }; 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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f855e7ca78sm56258705ad.106.2024.06.15.19.47.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 15 Jun 2024 19:47:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1718506037; x=1719110837; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=uaT4Xh3LINeUYOT/JS54yQJHfmaV3gzwWveVYqVCxGs=; b=UR9S0ABn+I/Rir074clhBVaKN4NsXEGKnRPiLNhdbtznwkLjID7+shbY4x5bzjN53O 7F63Fq72aDyVzq9UqNxiiFaamx5bDl0dueUYakjNvpevn7cyztA3sj1PwXQwDLzo/TGb BXiyaTnaasXOx1eCsNwJjKfKgBnBXNC4nrFk/86xYzqQmn2+CYNWUaFOI0iQxeuIrh1i vKwZGL/LU3rgCchjTo0c5s9zbr74ltUUQgAVAGPRWaEcw7KDxO6gIA3bjBb7WzPzwMwG +tKTf5Oy5epUGqiFDAYizBYaV9wk++QhuGXV2eHEx34IrfprH56h47fJ0+FPHzazn/wy yZ0Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1718506037; x=1719110837; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=uaT4Xh3LINeUYOT/JS54yQJHfmaV3gzwWveVYqVCxGs=; b=MRECVX05XX3AUVu4g0eqIlyi8ekDpyaBxRqbXLNwkJRV2KbiOJBPwVoG07GTqvVmFR 8eBhcqIYsVe3s9YFPBq140XH0cHURIa9LVuywbil1VLcAvV/DmYeu8p+v3IgAAa0kWyp Hj4OgFEia/vRZKjcZWf19G4vQ1WmQ7D/ygWlgXVCTrY5zxJuIFjIylUlg3L7hAcFxNOK yKKzkm6Sv7NiK20hvfIRLI7VqUMenLAyowrWx93Gl4TVsk8TKKpF7dNNH9cEJNR9MsLY 0idUiyNp6WlaPdGB20QG4k6u7krI/QFSvWWNGTE1+bWPgBJacKVSR72GiBdrHG3gCDvH q/Ig== X-Gm-Message-State: AOJu0Ywrq49dtNM8KT4YPJ7oTOu4snNwGyijUvHw9ov5Ca8hTZ6YV+1S pVC3iT8lnUtR2YKniPH74T3W5XjiIlzLprmF1H0rSdYmi3x/lqq9ad/1ymy1IjxKIP/CZY06tf5 TmqHzWbdrpPctlL6/OIkH/8inUEhIf2qzKbh93o6kkFudKY2QflbDTa8w+C9aycSVEp940exVPU hyPGeR0HU3aDWTrbeXEGAxcO/WYgg11NSfomhyQwE= X-Google-Smtp-Source: AGHT+IG3c4OeDjeJLhJPvtcRht2oOmNCpxHC4V5M9giqrlh1ui68fPFYedKuxCAnuLFa9jSlBa1z3A== X-Received: by 2002:a17:903:11cf:b0:1f6:1a86:37ba with SMTP id d9443c01a7336-1f8620ae5ccmr95840855ad.2.1718506036918; Sat, 15 Jun 2024 19:47:16 -0700 (PDT) From: frank.chang@sifive.com To: qemu-devel@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , qemu-riscv@nongnu.org (open list:RISC-V TCG CPUs), Frank Chang , Jerry Zhang Jian , Max Chou Subject: [PATCH v2 5/6] target/riscv: Add Zc extension implied rule Date: Sun, 16 Jun 2024 10:46:56 +0800 Message-ID: <20240616024657.17948-6-frank.chang@sifive.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240616024657.17948-1-frank.chang@sifive.com> References: <20240616024657.17948-1-frank.chang@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=frank.chang@sifive.com; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1718506115339100009 Content-Type: text/plain; charset="utf-8" From: Frank Chang Zc extension has special implied rules that need to be handled separately. Signed-off-by: Frank Chang Reviewed-by: Jerry Zhang Jian Tested-by: Max Chou Reviewed-by: Daniel Henrique Barboza --- target/riscv/tcg/tcg-cpu.c | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index f8d6371764..fe84d4402e 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -902,11 +902,45 @@ static void cpu_enable_implied_rule(RISCVCPU *cpu, } } =20 +/* Zc extension has special implied rules that need to be handled separate= ly. */ +static void cpu_enable_zc_implied_rules(RISCVCPU *cpu) +{ + RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(cpu); + CPURISCVState *env =3D &cpu->env; + + if (cpu->cfg.ext_zce) { + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcb), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmp), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmt), true); + + if (riscv_has_ext(env, RVF) && mcc->misa_mxl_max =3D=3D MXL_RV32) { + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true); + } + } + + /* Zca, Zcd and Zcf has a PRIV 1.12.0 restriction */ + if (riscv_has_ext(env, RVC) && env->priv_ver >=3D PRIV_VERSION_1_12_0)= { + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); + + if (riscv_has_ext(env, RVF) && mcc->misa_mxl_max =3D=3D MXL_RV32) { + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true); + } + + if (riscv_has_ext(env, RVD)) { + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcd), true); + } + } +} + static void riscv_cpu_enable_implied_rules(RISCVCPU *cpu) { RISCVCPUImpliedExtsRule *rule; int i; =20 + /* Enable the implied extensions for Zc. */ + cpu_enable_zc_implied_rules(cpu); + /* Enable the implied MISAs. */ for (i =3D 0; (rule =3D riscv_misa_implied_rules[i]); i++) { if (riscv_has_ext(&cpu->env, rule->ext)) { --=20 2.43.2 From nobody Mon Nov 25 01:37:50 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=sifive.com ARC-Seal: i=1; a=rsa-sha256; t=1718506114; cv=none; d=zohomail.com; s=zohoarc; b=croGXNkBK3zbFy964h0rNBmBXQfofw/YZ9+P/eqxHFSjr0gndyHU6y6RA5Mew43bl6wlScrEpch07XkUg0LECcPGCrt5CBUx0H+NEWE47D4I3uc1bjnf7eoF1EvirWOfNnbVQ7YevL5x9LFMpF5Sb7eVBb2BEjU1pxXx3GqPRQ4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1718506114; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=OmFiATPm95+4kWSDn9aSKWPJ0UC08eg4l8qOQUPIprs=; b=BIPBE+/OHYK+wB4uN0vO9pr40D35xImEnAyxWXP9aBB+AKpqonlOJ+PQeTojgxZ2KvVnnjLJhi8E0h2hdtvtuweNuU0yegY5t6DeJn/obD2vILThYvOwuQqFCavQ+B1hJ9bUKi9lt4EpGmM5bdtNpCqmzM4/m1e7e/3qd80Kg+M= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1718506114522142.86978911336553; Sat, 15 Jun 2024 19:48:34 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sIfvQ-0007TQ-P0; Sat, 15 Jun 2024 22:47:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sIfvP-0007Ss-LR for qemu-devel@nongnu.org; Sat, 15 Jun 2024 22:47:23 -0400 Received: from mail-oo1-xc32.google.com ([2607:f8b0:4864:20::c32]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sIfvN-0001j1-Rl for qemu-devel@nongnu.org; Sat, 15 Jun 2024 22:47:23 -0400 Received: by mail-oo1-xc32.google.com with SMTP id 006d021491bc7-5b9778bb7c8so1709906eaf.3 for ; Sat, 15 Jun 2024 19:47:21 -0700 (PDT) Received: from hsinchu16.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f855e7ca78sm56258705ad.106.2024.06.15.19.47.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 15 Jun 2024 19:47:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1718506039; x=1719110839; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=OmFiATPm95+4kWSDn9aSKWPJ0UC08eg4l8qOQUPIprs=; b=doSi+e5bf+4PZ61Y/x1a+hMeK85eEf6Npdz/8xPxJvvWJLQyexoOhwz8LEK7AmQA1k GpQuPYtbLq1TKRh3ERI/Y6A2mwvEizQJiY6RZudo5oHmJHH8sWeuengLZPguLzHSj4sL 4inBMTFSCWeZSSVZAM1baNdUCslQ+CvTiZBdte4Z9tI/9v1i0aCYvUEm7kdEMUDvyPmY ksXHK7gWJryMe9XgH2NhAdqjPV4FUck0wBfVyqC4vOZKn+/u8geAXUaahS1boG+dkTqe MpeSH8SEeQ4Vmg7AVHisG7NWxKEBP1ILhVKPWic8GVcmoH++Lli2ZkAICePRjbD5L4mB pV8w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1718506039; x=1719110839; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OmFiATPm95+4kWSDn9aSKWPJ0UC08eg4l8qOQUPIprs=; b=e2eK4aGNhZ0DCBSCjcCefpU8WRW2llCrTgTI1LwxTCt6YMBb7KghuzILAmavS+CY86 FEyAeZamj206CEBGrhQmTKywJZQszOkj9euT1v5X9HLZXkY/ans8KkrG0CZhykcaRXeE Ogh91LN1x1N6w44/NPU01ZXIfv249jzBvjxClI0K77KgnqOZdgYRnSzHx6vol1aPML0D CfVTBFnG8y/iSzANzEvOGWlbU73bJ3YAgI6oN+iqZCwwR5tmViDqpGq4N1cSdwsR9Nfp rlqnwBqZvw88lbKCkPTypQB+l49puS5tsT282HetVZWXVKsLrKIL7r+adaJ7+IaMmPQV 619Q== X-Gm-Message-State: AOJu0Yxi+kZAsdfThbQHXnSkRj7uXLguWlFdNzk/zBYvsafHKRlooO+N vQyjm8B433I1cB9dU54TGhyThev2S2eHzf+wH5hJJmchaOePfmnoUcXW9CTb5ANvfEIf9wTOciQ MhkxJaQ0hDzdnamTOch7sPBe+LbiOb5um6vRhiNc74zJlVb64DQ7xxYACaMufUjaaxsebRx53pX nspChTV1FKF+p2ZMPaddemr1plgGkgg7R6n3GRT+o= X-Google-Smtp-Source: AGHT+IGIGNdf8H4+ttp0asKeVEKhyFwPrQHuW9kxhEgoGo8whK873Nq6JJ5PFsWsbWxNvdO3db7VOw== X-Received: by 2002:a05:6358:938c:b0:19f:3ee1:d1c4 with SMTP id e5c5f4694b2df-19fa9dcf95dmr857367855d.2.1718506039371; Sat, 15 Jun 2024 19:47:19 -0700 (PDT) From: frank.chang@sifive.com To: qemu-devel@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , qemu-riscv@nongnu.org (open list:RISC-V TCG CPUs), Frank Chang , Jerry Zhang Jian , Max Chou Subject: [PATCH v2 6/6] target/riscv: Remove extension auto-update check statements Date: Sun, 16 Jun 2024 10:46:57 +0800 Message-ID: <20240616024657.17948-7-frank.chang@sifive.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240616024657.17948-1-frank.chang@sifive.com> References: <20240616024657.17948-1-frank.chang@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::c32; envelope-from=frank.chang@sifive.com; helo=mail-oo1-xc32.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1718506115345100010 Content-Type: text/plain; charset="utf-8" From: Frank Chang Remove the old-fashioned extension auto-update check statements as they are replaced by the extension implied rules. Signed-off-by: Frank Chang Reviewed-by: Jerry Zhang Jian Tested-by: Max Chou Reviewed-by: Daniel Henrique Barboza --- target/riscv/tcg/tcg-cpu.c | 119 ------------------------------------- 1 file changed, 119 deletions(-) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index fe84d4402e..94875c8ec9 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -468,10 +468,6 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, = Error **errp) return; } =20 - if (cpu->cfg.ext_zfh) { - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zfhmin), true); - } - if (cpu->cfg.ext_zfhmin && !riscv_has_ext(env, RVF)) { error_setg(errp, "Zfh/Zfhmin extensions require F extension"); return; @@ -493,9 +489,6 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, E= rror **errp) error_propagate(errp, local_err); return; } - - /* The V vector extension depends on the Zve64d extension */ - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64d), true); } =20 /* The Zve64d extension depends on the Zve64f extension */ @@ -504,18 +497,6 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, = Error **errp) error_setg(errp, "Zve64d/V extensions require D extension"); return; } - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64f), true); - } - - /* The Zve64f extension depends on the Zve64x and Zve32f extensions */ - if (cpu->cfg.ext_zve64f) { - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64x), true); - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32f), true); - } - - /* The Zve64x extension depends on the Zve32x extension */ - if (cpu->cfg.ext_zve64x) { - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32x), true); } =20 /* The Zve32f extension depends on the Zve32x extension */ @@ -524,11 +505,6 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, = Error **errp) error_setg(errp, "Zve32f/Zve64f extensions require F extension= "); return; } - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32x), true); - } - - if (cpu->cfg.ext_zvfh) { - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvfhmin), true); } =20 if (cpu->cfg.ext_zvfhmin && !cpu->cfg.ext_zve32f) { @@ -551,11 +527,6 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, = Error **errp) return; } =20 - /* Set the ISA extensions, checks should have happened above */ - if (cpu->cfg.ext_zhinx) { - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); - } - if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfi= nx) { error_setg(errp, "Zdinx/Zhinx/Zhinxmin extensions require Zfinx"); return; @@ -573,27 +544,6 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, = Error **errp) } } =20 - if (cpu->cfg.ext_zce) { - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcb), true); - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmp), true); - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmt), true); - if (riscv_has_ext(env, RVF) && mcc->misa_mxl_max =3D=3D MXL_RV32) { - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true); - } - } - - /* zca, zcd and zcf has a PRIV 1.12.0 restriction */ - if (riscv_has_ext(env, RVC) && env->priv_ver >=3D PRIV_VERSION_1_12_0)= { - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); - if (riscv_has_ext(env, RVF) && mcc->misa_mxl_max =3D=3D MXL_RV32) { - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true); - } - if (riscv_has_ext(env, RVD)) { - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcd), true); - } - } - if (mcc->misa_mxl_max !=3D MXL_RV32 && cpu->cfg.ext_zcf) { error_setg(errp, "Zcf extension is only relevant to RV32"); return; @@ -627,52 +577,6 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, = Error **errp) return; } =20 - /* - * Shorthand vector crypto extensions - */ - if (cpu->cfg.ext_zvknc) { - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkn), true); - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true); - } - - if (cpu->cfg.ext_zvkng) { - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkn), true); - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkg), true); - } - - if (cpu->cfg.ext_zvkn) { - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkned), true); - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvknhb), true); - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkb), true); - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkt), true); - } - - if (cpu->cfg.ext_zvksc) { - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvks), true); - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true); - } - - if (cpu->cfg.ext_zvksg) { - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvks), true); - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkg), true); - } - - if (cpu->cfg.ext_zvks) { - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvksed), true); - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvksh), true); - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkb), true); - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkt), true); - } - - if (cpu->cfg.ext_zvkt) { - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbb), true); - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true); - } - - if (cpu->cfg.ext_zvbb) { - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkb), true); - } - if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkb || cpu->cfg.ext_zvkg || cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed= || cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32x) { @@ -688,29 +592,6 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, = Error **errp) return; } =20 - if (cpu->cfg.ext_zk) { - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkn), true); - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkr), true); - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkt), true); - } - - if (cpu->cfg.ext_zkn) { - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkb), true); - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkc), true); - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkx), true); - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkne), true); - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zknd), true); - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zknh), true); - } - - if (cpu->cfg.ext_zks) { - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkb), true); - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkc), true); - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkx), true); - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zksed), true); - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zksh), true); - } - if (cpu->cfg.ext_zicntr && !cpu->cfg.ext_zicsr) { if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zicntr))) { error_setg(errp, "zicntr requires zicsr"); --=20 2.43.2