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Chardev frontends should be named as "dcc" inorder to connect to this interface. Signed-off-by: Sai Pavan Boddu --- target/arm/cpu.h | 11 +++++ target/arm/internals.h | 4 ++ target/arm/debug-dcc.c | 99 ++++++++++++++++++++++++++++++++++++++++++ target/arm/helper.c | 3 ++ target/arm/meson.build | 1 + 5 files changed, 118 insertions(+) create mode 100644 target/arm/debug-dcc.c diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 3841359d0f..6b3cb8e70e 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -30,6 +30,8 @@ #include "qapi/qapi-types-common.h" #include "target/arm/multiprocessing.h" #include "target/arm/gtimer.h" +#include "chardev/char.h" +#include "chardev/char-fe.h" =20 #ifdef TARGET_AARCH64 #define KVM_HAVE_MCE_INJECTION 1 @@ -523,6 +525,11 @@ typedef struct CPUArchState { =20 /* NV2 register */ uint64_t vncr_el2; + /* + * Debug Trace regsiters + */ + uint32_t dbgdtr_tx; + uint32_t dbgdtr_rx; } cp15; =20 struct { @@ -1097,6 +1104,9 @@ struct ArchCPU { =20 /* Generic timer counter frequency, in Hz */ uint64_t gt_cntfrq_hz; + + /* dcc chardev */ + CharBackend dcc; }; =20 typedef struct ARMCPUInfo { @@ -2388,6 +2398,7 @@ enum arm_features { * CPU types added in future. */ ARM_FEATURE_BACKCOMPAT_CNTFRQ, /* 62.5MHz timer default */ + ARM_FEATURE_DCC, }; =20 static inline int arm_feature(CPUARMState *env, int feature) diff --git a/target/arm/internals.h b/target/arm/internals.h index 11b5da2562..2fa797c5df 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1778,4 +1778,8 @@ uint64_t gt_get_countervalue(CPUARMState *env); * and CNTVCT_EL0 (this will be either 0 or the value of CNTVOFF_EL2). */ uint64_t gt_virt_cnt_offset(CPUARMState *env); +/* + * Initialise Coresight Debug interface + */ +void arm_dcc_init(ARMCPU *cpu); #endif diff --git a/target/arm/debug-dcc.c b/target/arm/debug-dcc.c new file mode 100644 index 0000000000..9144b54994 --- /dev/null +++ b/target/arm/debug-dcc.c @@ -0,0 +1,99 @@ +#include "qemu/osdep.h" +#include "cpu.h" +#include "internals.h" +#include "cpregs.h" +#include "chardev/char-fe.h" + +#define MDCCSR_EL0_RXFULL_MASK (1 << 30) +#define MDCCSR_EL0_TXFULL_MASK (1 << 29) + +static void debug_dcc_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + ARMCPU *cpu =3D ri->opaque; + env->cp15.dbgdtr_tx =3D value; + + if (qemu_chr_fe_get_driver(&cpu->dcc)) { + /* + * Usually dcc is used for putc/getc calls which expect only + * 1 byte from external debugger. + * TODO: This needs to be generalized for other use-cases. + */ + qemu_chr_fe_write_all(&cpu->dcc, (uint8_t *)&env->cp15.dbgdtr_tx, = 1); + } +} + +static uint64_t debug_dcc_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + uint32_t ret =3D 0; + ARMCPU *cpu =3D ri->opaque; + + if (env->cp15.mdscr_el1 & MDCCSR_EL0_RXFULL_MASK) { + ret =3D env->cp15.dbgdtr_rx; + env->cp15.dbgdtr_rx =3D 0; + env->cp15.mdscr_el1 &=3D ~MDCCSR_EL0_RXFULL_MASK; + qemu_chr_fe_accept_input(&cpu->dcc); + } + return ret; +} + +static const ARMCPRegInfo dcc_cp_reginfo[] =3D { + /* DBGDTRTX_EL0/DBGDTRRX_EL0 depend on direction */ + { .name =3D "DBGDTR_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 2, .opc1 =3D 3, .crn =3D 0, .crm =3D 5, .opc2 =3D 0, + .access =3D PL0_RW, .writefn =3D debug_dcc_write, + .readfn =3D debug_dcc_read, + .type =3D ARM_CP_OVERRIDE, .resetvalue =3D 0 }, + /* DBGDTRTXint/DBGDTRRXint depend on direction */ + { .name =3D "DBGDTRint", .state =3D ARM_CP_STATE_AA32, .cp =3D 14, + .opc1 =3D 0, .crn =3D 0, .crm =3D 5, .opc2 =3D 0, + .access =3D PL0_RW, .writefn =3D debug_dcc_write, + .readfn =3D debug_dcc_read, + .type =3D ARM_CP_OVERRIDE, .resetvalue =3D 0 }, +}; + + +static int dcc_chr_can_read(void *opaque) +{ + ARMCPU *cpu =3D opaque; + CPUARMState *env =3D &cpu->env; + + if (!(env->cp15.mdscr_el1 & MDCCSR_EL0_RXFULL_MASK)) { + /* + * Usually dcc is used for putc/getc calls which expect only + * 1 byte from external debugger. + * TODO: This needs to be generalized for other use-cases. + */ + return 1; + } + + return 0; +} + +static void dcc_chr_read(void *opaque, const uint8_t *buf, int size) +{ + ARMCPU *cpu =3D opaque; + CPUARMState *env =3D &cpu->env; + + env->cp15.dbgdtr_rx =3D *buf; + env->cp15.mdscr_el1 |=3D MDCCSR_EL0_RXFULL_MASK; +} + +void arm_dcc_init(ARMCPU *cpu) +{ + Chardev *chr; + char *dcc_name; + CPUState *p =3D CPU(cpu); + + dcc_name =3D g_strdup_printf("dcc%d", p->cpu_index); + chr =3D qemu_chr_find(dcc_name); + define_arm_cp_regs_with_opaque(cpu, dcc_cp_reginfo, cpu); + if (chr) { + qemu_chr_fe_init(&cpu->dcc, chr, NULL); + qemu_chr_fe_set_handlers(&cpu->dcc, + dcc_chr_can_read, + dcc_chr_read, + NULL, NULL, cpu, NULL, true); + } + g_free(dcc_name); +} diff --git a/target/arm/helper.c b/target/arm/helper.c index ce31957235..2b594f91cb 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9268,6 +9268,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) } } =20 + if (arm_feature(&cpu->env, ARM_FEATURE_DCC)) { + arm_dcc_init(cpu); + } /* * Register the base EL2 cpregs. * Pre v8, these registers are implemented only as part of the diff --git a/target/arm/meson.build b/target/arm/meson.build index 2e10464dbb..3ee38c6b45 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -5,6 +5,7 @@ arm_ss.add(files( 'gdbstub.c', 'helper.c', 'vfp_helper.c', + 'debug-dcc.c', )) arm_ss.add(zlib) =20 --=20 2.34.1 From nobody Mon Nov 25 01:40:16 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=amd.com); 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Signed-off-by: Sai Pavan Boddu --- target/arm/cpu64.c | 1 + target/arm/tcg/cpu32.c | 1 + 2 files changed, 2 insertions(+) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 262a1d6c0b..e39740303b 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -667,6 +667,7 @@ static void aarch64_a53_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_EL2); set_feature(&cpu->env, ARM_FEATURE_EL3); set_feature(&cpu->env, ARM_FEATURE_PMU); + set_feature(&cpu->env, ARM_FEATURE_DCC); cpu->kvm_target =3D QEMU_KVM_ARM_TARGET_CORTEX_A53; cpu->midr =3D 0x410fd034; cpu->revidr =3D 0x00000100; diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c index bdd82d912a..b0ef51a9bf 100644 --- a/target/arm/tcg/cpu32.c +++ b/target/arm/tcg/cpu32.c @@ -562,6 +562,7 @@ static void cortex_r5_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V7MP); set_feature(&cpu->env, ARM_FEATURE_PMSA); set_feature(&cpu->env, ARM_FEATURE_PMU); + set_feature(&cpu->env, ARM_FEATURE_DCC); cpu->midr =3D 0x411fc153; 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Signed-off-by: Sai Pavan Boddu --- target/arm/debug_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index 7d856acddf..5deafa4d1f 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -970,7 +970,7 @@ static const ARMCPRegInfo debug_cp_reginfo[] =3D { { .name =3D "MDCCSR_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 2, .opc1 =3D 3, .crn =3D 0, .crm =3D 1, .opc2 =3D 0, .access =3D PL0_R, .accessfn =3D access_tdcc, - .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + .fieldoffset =3D offsetof(CPUARMState, cp15.mdscr_el1)}, /* Xilinx */ /* * These registers belong to the Debug Communications Channel, * which is not implemented. However we implement RAZ/WI behaviour --=20 2.34.1