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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1718350070; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=XP/iTr/BVBIoYxsQ+3kqlBLFtRaXOsgv0fgawDKkxnQ=; b=Qy20UWxXqc4u/sjj9x/Jf9HkP84bqYdzDgrkQn/LdnkSY0zfqFf2+TA3AN/aNUX0zW2jEX sxTz+3CQVCaptRCWtz/oIM9GlQuVaFdG+uD6xqNBNBYWszphMnmkJoG1fhY1CrD2I86mZu tAoxLyzA3mkMUe0x00qQ4f/cMIiAuzk= X-MC-Unique: 2Rry6W_pNuSvUUD65gRb2Q-1 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jamin Lin , Troy Lee , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 08/19] aspeed/smc: support dma start length and 1 byte length unit Date: Fri, 14 Jun 2024 09:26:09 +0200 Message-ID: <20240614072620.1262053-9-clg@redhat.com> In-Reply-To: <20240614072620.1262053-1-clg@redhat.com> References: <20240614072620.1262053-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: 11 X-Spam_score: 1.1 X-Spam_bar: + X-Spam_report: (1.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.145, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1718350102267100011 From: Jamin Lin DMA length is from 1 byte to 32MB for AST2600 and AST10x0 and DMA length is from 4 bytes to 32MB for AST2500. In other words, if "R_DMA_LEN" is 0, it should move at least 1 byte data for AST2600 and AST10x0 and 4 bytes data for AST2500. To support all ASPEED SOCs, adds dma_start_length parameter to store the start length, add helper routines function to compute the dma length and update DMA_LENGTH mask to "1FFFFFF" to support dma 1 byte length unit for AST2600 and AST1030. Currently, only supports dma length 4 bytes aligned. Signed-off-by: Troy Lee Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater --- include/hw/ssi/aspeed_smc.h | 1 + hw/ssi/aspeed_smc.c | 43 ++++++++++++++++++++++++++++++------- 2 files changed, 36 insertions(+), 8 deletions(-) diff --git a/include/hw/ssi/aspeed_smc.h b/include/hw/ssi/aspeed_smc.h index 8791cc0ecb11..d305ce2e2fea 100644 --- a/include/hw/ssi/aspeed_smc.h +++ b/include/hw/ssi/aspeed_smc.h @@ -107,6 +107,7 @@ struct AspeedSMCClass { uint32_t features; hwaddr dma_flash_mask; hwaddr dma_dram_mask; + uint32_t dma_start_length; uint32_t nregs; uint32_t (*segment_to_reg)(const AspeedSMCState *s, const AspeedSegments *seg); diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c index fe1cd96b803a..0b8488a113db 100644 --- a/hw/ssi/aspeed_smc.c +++ b/hw/ssi/aspeed_smc.c @@ -178,13 +178,17 @@ * DMA flash addresses should be 4 bytes aligned and the valid address * range is 0x20000000 - 0x2FFFFFFF. * - * DMA length is from 4 bytes to 32MB + * DMA length is from 4 bytes to 32MB (AST2500) * 0: 4 bytes - * 0x7FFFFF: 32M bytes + * 0x1FFFFFC: 32M bytes + * + * DMA length is from 1 byte to 32MB (AST2600, AST10x0) + * 0: 1 byte + * 0x1FFFFFF: 32M bytes */ #define DMA_DRAM_ADDR(asc, val) ((val) & (asc)->dma_dram_mask) #define DMA_FLASH_ADDR(asc, val) ((val) & (asc)->dma_flash_mask) -#define DMA_LENGTH(val) ((val) & 0x01FFFFFC) +#define DMA_LENGTH(val) ((val) & 0x01FFFFFF) =20 /* Flash opcodes. */ #define SPI_OP_READ 0x03 /* Read data bytes (low frequency) */ @@ -843,6 +847,13 @@ static bool aspeed_smc_inject_read_failure(AspeedSMCSt= ate *s) } } =20 +static uint32_t aspeed_smc_dma_len(AspeedSMCState *s) +{ + AspeedSMCClass *asc =3D ASPEED_SMC_GET_CLASS(s); + + return QEMU_ALIGN_UP(s->regs[R_DMA_LEN] + asc->dma_start_length, 4); +} + /* * Accumulate the result of the reads to provide a checksum that will * be used to validate the read timing settings. @@ -850,6 +861,7 @@ static bool aspeed_smc_inject_read_failure(AspeedSMCSta= te *s) static void aspeed_smc_dma_checksum(AspeedSMCState *s) { MemTxResult result; + uint32_t dma_len; uint32_t data; =20 if (s->regs[R_DMA_CTRL] & DMA_CTRL_WRITE) { @@ -861,7 +873,9 @@ static void aspeed_smc_dma_checksum(AspeedSMCState *s) aspeed_smc_dma_calibration(s); } =20 - while (s->regs[R_DMA_LEN]) { + dma_len =3D aspeed_smc_dma_len(s); + + while (dma_len) { data =3D address_space_ldl_le(&s->flash_as, s->regs[R_DMA_FLASH_AD= DR], MEMTXATTRS_UNSPECIFIED, &result); if (result !=3D MEMTX_OK) { @@ -877,7 +891,8 @@ static void aspeed_smc_dma_checksum(AspeedSMCState *s) */ s->regs[R_DMA_CHECKSUM] +=3D data; s->regs[R_DMA_FLASH_ADDR] +=3D 4; - s->regs[R_DMA_LEN] -=3D 4; + dma_len -=3D 4; + s->regs[R_DMA_LEN] =3D dma_len; } =20 if (s->inject_failure && aspeed_smc_inject_read_failure(s)) { @@ -889,14 +904,17 @@ static void aspeed_smc_dma_checksum(AspeedSMCState *s) static void aspeed_smc_dma_rw(AspeedSMCState *s) { MemTxResult result; + uint32_t dma_len; uint32_t data; =20 + dma_len =3D aspeed_smc_dma_len(s); + trace_aspeed_smc_dma_rw(s->regs[R_DMA_CTRL] & DMA_CTRL_WRITE ? "write" : "read", s->regs[R_DMA_FLASH_ADDR], s->regs[R_DMA_DRAM_ADDR], - s->regs[R_DMA_LEN]); - while (s->regs[R_DMA_LEN]) { + dma_len); + while (dma_len) { if (s->regs[R_DMA_CTRL] & DMA_CTRL_WRITE) { data =3D address_space_ldl_le(&s->dram_as, s->regs[R_DMA_DRAM_= ADDR], MEMTXATTRS_UNSPECIFIED, &result); @@ -937,7 +955,8 @@ static void aspeed_smc_dma_rw(AspeedSMCState *s) */ s->regs[R_DMA_FLASH_ADDR] +=3D 4; s->regs[R_DMA_DRAM_ADDR] +=3D 4; - s->regs[R_DMA_LEN] -=3D 4; + dma_len -=3D 4; + s->regs[R_DMA_LEN] =3D dma_len; s->regs[R_DMA_CHECKSUM] +=3D data; } } @@ -1382,6 +1401,7 @@ static void aspeed_2400_fmc_class_init(ObjectClass *k= lass, void *data) asc->features =3D ASPEED_SMC_FEATURE_DMA; asc->dma_flash_mask =3D 0x0FFFFFFC; asc->dma_dram_mask =3D 0x1FFFFFFC; + asc->dma_start_length =3D 4; asc->nregs =3D ASPEED_SMC_R_MAX; asc->segment_to_reg =3D aspeed_smc_segment_to_reg; asc->reg_to_segment =3D aspeed_smc_reg_to_segment; @@ -1465,6 +1485,7 @@ static void aspeed_2500_fmc_class_init(ObjectClass *k= lass, void *data) asc->features =3D ASPEED_SMC_FEATURE_DMA; asc->dma_flash_mask =3D 0x0FFFFFFC; asc->dma_dram_mask =3D 0x3FFFFFFC; + asc->dma_start_length =3D 4; asc->nregs =3D ASPEED_SMC_R_MAX; asc->segment_to_reg =3D aspeed_smc_segment_to_reg; asc->reg_to_segment =3D aspeed_smc_reg_to_segment; @@ -1621,6 +1642,7 @@ static void aspeed_2600_fmc_class_init(ObjectClass *k= lass, void *data) ASPEED_SMC_FEATURE_WDT_CONTROL; asc->dma_flash_mask =3D 0x0FFFFFFC; asc->dma_dram_mask =3D 0x3FFFFFFC; + asc->dma_start_length =3D 1; asc->nregs =3D ASPEED_SMC_R_MAX; asc->segment_to_reg =3D aspeed_2600_smc_segment_to_reg; asc->reg_to_segment =3D aspeed_2600_smc_reg_to_segment; @@ -1659,6 +1681,7 @@ static void aspeed_2600_spi1_class_init(ObjectClass *= klass, void *data) ASPEED_SMC_FEATURE_DMA_GRANT; asc->dma_flash_mask =3D 0x0FFFFFFC; asc->dma_dram_mask =3D 0x3FFFFFFC; + asc->dma_start_length =3D 1; asc->nregs =3D ASPEED_SMC_R_MAX; asc->segment_to_reg =3D aspeed_2600_smc_segment_to_reg; asc->reg_to_segment =3D aspeed_2600_smc_reg_to_segment; @@ -1698,6 +1721,7 @@ static void aspeed_2600_spi2_class_init(ObjectClass *= klass, void *data) ASPEED_SMC_FEATURE_DMA_GRANT; asc->dma_flash_mask =3D 0x0FFFFFFC; asc->dma_dram_mask =3D 0x3FFFFFFC; + asc->dma_start_length =3D 1; asc->nregs =3D ASPEED_SMC_R_MAX; asc->segment_to_reg =3D aspeed_2600_smc_segment_to_reg; asc->reg_to_segment =3D aspeed_2600_smc_reg_to_segment; @@ -1779,6 +1803,7 @@ static void aspeed_1030_fmc_class_init(ObjectClass *k= lass, void *data) asc->features =3D ASPEED_SMC_FEATURE_DMA; asc->dma_flash_mask =3D 0x0FFFFFFC; asc->dma_dram_mask =3D 0x000BFFFC; + asc->dma_start_length =3D 1; asc->nregs =3D ASPEED_SMC_R_MAX; asc->segment_to_reg =3D aspeed_1030_smc_segment_to_reg; asc->reg_to_segment =3D aspeed_1030_smc_reg_to_segment; @@ -1816,6 +1841,7 @@ static void aspeed_1030_spi1_class_init(ObjectClass *= klass, void *data) asc->features =3D ASPEED_SMC_FEATURE_DMA; asc->dma_flash_mask =3D 0x0FFFFFFC; asc->dma_dram_mask =3D 0x000BFFFC; + asc->dma_start_length =3D 1; asc->nregs =3D ASPEED_SMC_R_MAX; asc->segment_to_reg =3D aspeed_2600_smc_segment_to_reg; asc->reg_to_segment =3D aspeed_2600_smc_reg_to_segment; @@ -1852,6 +1878,7 @@ static void aspeed_1030_spi2_class_init(ObjectClass *= klass, void *data) asc->features =3D ASPEED_SMC_FEATURE_DMA; asc->dma_flash_mask =3D 0x0FFFFFFC; asc->dma_dram_mask =3D 0x000BFFFC; + asc->dma_start_length =3D 1; asc->nregs =3D ASPEED_SMC_R_MAX; asc->segment_to_reg =3D aspeed_2600_smc_segment_to_reg; asc->reg_to_segment =3D aspeed_2600_smc_reg_to_segment; --=20 2.45.2