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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1718350057; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=AYWGjfqdWTHN73mpwY5Vg/n4nswDcBeE67iGIGD6bgk=; b=gHSmv0/VsOk2lrBKD9ekG+SLki0YPWNHb1J2ry/um6xSkmKEaG08+T2014MK4jWVROCp2E Uf4YJ9lBE6L8F/MIiHuXW1wQI7wuTFCbJwPLC77BcDKnm+vstFNFQIFUWdJHyPcgYsoMyn LJXNxduzBYq3ugmyVMXeB9uRI5R2yBQ= X-MC-Unique: bFlG5q9YMfGOxBAEzY7hWA-1 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jamin Lin , Troy Lee , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 03/19] aspeed/sli: Add AST2700 support Date: Fri, 14 Jun 2024 09:26:04 +0200 Message-ID: <20240614072620.1262053-4-clg@redhat.com> In-Reply-To: <20240614072620.1262053-1-clg@redhat.com> References: <20240614072620.1262053-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: 11 X-Spam_score: 1.1 X-Spam_bar: + X-Spam_report: (1.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.145, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1718350198524100008 From: Jamin Lin AST2700 SLI engine is designed to accelerate the throughput between cross-die connections. It have CPU_SLI at CPU die and IO_SLI at IO die. Introduce dummy AST2700 SLI and SLIIO models. Signed-off-by: Troy Lee Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater --- include/hw/misc/aspeed_sli.h | 27 ++++++ hw/misc/aspeed_sli.c | 177 +++++++++++++++++++++++++++++++++++ hw/misc/meson.build | 3 +- hw/misc/trace-events | 7 ++ 4 files changed, 213 insertions(+), 1 deletion(-) create mode 100644 include/hw/misc/aspeed_sli.h create mode 100644 hw/misc/aspeed_sli.c diff --git a/include/hw/misc/aspeed_sli.h b/include/hw/misc/aspeed_sli.h new file mode 100644 index 000000000000..23f346ab934b --- /dev/null +++ b/include/hw/misc/aspeed_sli.h @@ -0,0 +1,27 @@ +/* + * ASPEED SLI Controller + * + * Copyright (C) 2024 ASPEED Technology Inc. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#ifndef ASPEED_SLI_H +#define ASPEED_SLI_H + +#include "hw/sysbus.h" + +#define TYPE_ASPEED_SLI "aspeed.sli" +#define TYPE_ASPEED_2700_SLI TYPE_ASPEED_SLI "-ast2700" +#define TYPE_ASPEED_2700_SLIIO TYPE_ASPEED_SLI "io" "-ast2700" +OBJECT_DECLARE_SIMPLE_TYPE(AspeedSLIState, ASPEED_SLI) + +#define ASPEED_SLI_NR_REGS (0x500 >> 2) + +struct AspeedSLIState { + SysBusDevice parent; + MemoryRegion iomem; + + uint32_t regs[ASPEED_SLI_NR_REGS]; +}; + +#endif /* ASPEED_SLI_H */ diff --git a/hw/misc/aspeed_sli.c b/hw/misc/aspeed_sli.c new file mode 100644 index 000000000000..fe720ead5094 --- /dev/null +++ b/hw/misc/aspeed_sli.c @@ -0,0 +1,177 @@ +/* + * ASPEED SLI Controller + * + * Copyright (C) 2024 ASPEED Technology Inc. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qemu/error-report.h" +#include "hw/qdev-properties.h" +#include "hw/misc/aspeed_sli.h" +#include "qapi/error.h" +#include "migration/vmstate.h" +#include "trace.h" + +#define SLI_REGION_SIZE 0x500 +#define TO_REG(addr) ((addr) >> 2) + +static uint64_t aspeed_sli_read(void *opaque, hwaddr addr, unsigned int si= ze) +{ + AspeedSLIState *s =3D ASPEED_SLI(opaque); + int reg =3D TO_REG(addr); + + if (reg >=3D ARRAY_SIZE(s->regs)) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "= \n", + __func__, addr); + return 0; + } + + trace_aspeed_sli_read(addr, size, s->regs[reg]); + return s->regs[reg]; +} + +static void aspeed_sli_write(void *opaque, hwaddr addr, uint64_t data, + unsigned int size) +{ + AspeedSLIState *s =3D ASPEED_SLI(opaque); + int reg =3D TO_REG(addr); + + if (reg >=3D ARRAY_SIZE(s->regs)) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx = "\n", + __func__, addr); + return; + } + + trace_aspeed_sli_write(addr, size, data); + s->regs[reg] =3D data; +} + +static uint64_t aspeed_sliio_read(void *opaque, hwaddr addr, unsigned int = size) +{ + AspeedSLIState *s =3D ASPEED_SLI(opaque); + int reg =3D TO_REG(addr); + + if (reg >=3D ARRAY_SIZE(s->regs)) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "= \n", + __func__, addr); + return 0; + } + + trace_aspeed_sliio_read(addr, size, s->regs[reg]); + return s->regs[reg]; +} + +static void aspeed_sliio_write(void *opaque, hwaddr addr, uint64_t data, + unsigned int size) +{ + AspeedSLIState *s =3D ASPEED_SLI(opaque); + int reg =3D TO_REG(addr); + + if (reg >=3D ARRAY_SIZE(s->regs)) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx = "\n", + __func__, addr); + return; + } + + trace_aspeed_sliio_write(addr, size, data); + s->regs[reg] =3D data; +} + +static const MemoryRegionOps aspeed_sli_ops =3D { + .read =3D aspeed_sli_read, + .write =3D aspeed_sli_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 4, + }, +}; + +static const MemoryRegionOps aspeed_sliio_ops =3D { + .read =3D aspeed_sliio_read, + .write =3D aspeed_sliio_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 4, + }, +}; + +static void aspeed_sli_realize(DeviceState *dev, Error **errp) +{ + AspeedSLIState *s =3D ASPEED_SLI(dev); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); + + memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_sli_ops, s, + TYPE_ASPEED_SLI, SLI_REGION_SIZE); + sysbus_init_mmio(sbd, &s->iomem); +} + +static void aspeed_sliio_realize(DeviceState *dev, Error **errp) +{ + AspeedSLIState *s =3D ASPEED_SLI(dev); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); + + memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_sliio_ops, s, + TYPE_ASPEED_SLI, SLI_REGION_SIZE); + sysbus_init_mmio(sbd, &s->iomem); +} + +static void aspeed_sli_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->desc =3D "Aspeed SLI Controller"; + dc->realize =3D aspeed_sli_realize; +} + +static const TypeInfo aspeed_sli_info =3D { + .name =3D TYPE_ASPEED_SLI, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(AspeedSLIState), + .class_init =3D aspeed_sli_class_init, + .abstract =3D true, +}; + +static void aspeed_2700_sli_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->desc =3D "AST2700 SLI Controller"; +} + +static void aspeed_2700_sliio_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->desc =3D "AST2700 I/O SLI Controller"; + dc->realize =3D aspeed_sliio_realize; +} + +static const TypeInfo aspeed_2700_sli_info =3D { + .name =3D TYPE_ASPEED_2700_SLI, + .parent =3D TYPE_ASPEED_SLI, + .class_init =3D aspeed_2700_sli_class_init, +}; + +static const TypeInfo aspeed_2700_sliio_info =3D { + .name =3D TYPE_ASPEED_2700_SLIIO, + .parent =3D TYPE_ASPEED_SLI, + .class_init =3D aspeed_2700_sliio_class_init, +}; + +static void aspeed_sli_register_types(void) +{ + type_register_static(&aspeed_sli_info); + type_register_static(&aspeed_2700_sli_info); + type_register_static(&aspeed_2700_sliio_info); +} + +type_init(aspeed_sli_register_types); diff --git a/hw/misc/meson.build b/hw/misc/meson.build index 86596a388812..2ca8717be286 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -136,7 +136,8 @@ system_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files( 'aspeed_sbc.c', 'aspeed_sdmc.c', 'aspeed_xdma.c', - 'aspeed_peci.c')) + 'aspeed_peci.c', + 'aspeed_sli.c')) =20 system_ss.add(when: 'CONFIG_MSF2', if_true: files('msf2-sysreg.c')) system_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_rng.c')) diff --git a/hw/misc/trace-events b/hw/misc/trace-events index 5d241cb40aab..e13b64822110 100644 --- a/hw/misc/trace-events +++ b/hw/misc/trace-events @@ -351,3 +351,10 @@ djmemc_write(int reg, uint64_t value, unsigned int siz= e) "reg=3D0x%x value=3D0x%"PRI # iosb.c iosb_read(int reg, uint64_t value, unsigned int size) "reg=3D0x%x value=3D= 0x%"PRIx64" size=3D%u" iosb_write(int reg, uint64_t value, unsigned int size) "reg=3D0x%x value= =3D0x%"PRIx64" size=3D%u" + +# aspeed_sli.c +aspeed_sli_write(uint64_t offset, unsigned int size, uint32_t data) "To 0x= %" PRIx64 " of size %u: 0x%" PRIx32 +aspeed_sli_read(uint64_t offset, unsigned int size, uint32_t data) "To 0x%= " PRIx64 " of size %u: 0x%" PRIx32 +aspeed_sliio_write(uint64_t offset, unsigned int size, uint32_t data) "To = 0x%" PRIx64 " of size %u: 0x%" PRIx32 +aspeed_sliio_read(uint64_t offset, unsigned int size, uint32_t data) "To 0= x%" PRIx64 " of size %u: 0x%" PRIx32 + --=20 2.45.2