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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1718350078; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=mHYjj6xTVqULwYhf+vn1Jxw3e4hRDsjf++C3P7WZwn0=; b=eRDI5fRpV/9uqX9e9lIPET00mqt4CgaNKKgc6OYA3sKCsxupFsIBGBRcHA6Ta56pvOAp9u LE0SAgzKIRBtKCpbS+T6txrgL5XJ8/76vfknRsodHeos1Ddw9kj5deBsrEtRjcixTt6bUf bwRMBM2cZMglYziEin5HP4GZTXivLrA= X-MC-Unique: HLuNhVBhMkeXczyMOLB5bg-1 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jamin Lin , Troy Lee , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 11/19] aspeed/smc: Add AST2700 support Date: Fri, 14 Jun 2024 09:26:12 +0200 Message-ID: <20240614072620.1262053-12-clg@redhat.com> In-Reply-To: <20240614072620.1262053-1-clg@redhat.com> References: <20240614072620.1262053-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: 11 X-Spam_score: 1.1 X-Spam_bar: + X-Spam_report: (1.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.145, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1718350113154100001 From: Jamin Lin AST2700 fmc/spi controller's address decoding unit is 64KB and only bits [31:16] are used for decoding. Introduce seg_to_reg and reg_to_seg handlers for ast2700 fmc/spi controller. In addition, adds ast2700 fmc, spi0, spi1, and spi2 class init handler. AST2700 is a 64 bits quad core CPUs(Cortex-a35). Introduce a new "aspeed_2700_smc_flash_ops" and set its valid "max_access_size" 8 for 64 bits data format access. Signed-off-by: Troy Lee Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater --- hw/ssi/aspeed_smc.c | 234 +++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 233 insertions(+), 1 deletion(-) diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c index 129d06690d36..49205ab76d38 100644 --- a/hw/ssi/aspeed_smc.c +++ b/hw/ssi/aspeed_smc.c @@ -185,7 +185,7 @@ * 0: 4 bytes * 0x1FFFFFC: 32M bytes * - * DMA length is from 1 byte to 32MB (AST2600, AST10x0) + * DMA length is from 1 byte to 32MB (AST2600, AST10x0 and AST2700) * 0: 1 byte * 0x1FFFFFF: 32M bytes */ @@ -1938,6 +1938,234 @@ static const TypeInfo aspeed_1030_spi2_info =3D { .class_init =3D aspeed_1030_spi2_class_init, }; =20 +/* + * The FMC Segment Registers of the AST2700 have a 64KB unit. + * Only bits [31:16] are used for decoding. + */ +#define AST2700_SEG_ADDR_MASK 0xffff0000 + +static uint32_t aspeed_2700_smc_segment_to_reg(const AspeedSMCState *s, + const AspeedSegments *seg) +{ + uint32_t reg =3D 0; + + /* Disabled segments have a nil register */ + if (!seg->size) { + return 0; + } + + reg |=3D (seg->addr & AST2700_SEG_ADDR_MASK) >> 16; /* start offset */ + reg |=3D (seg->addr + seg->size - 1) & AST2700_SEG_ADDR_MASK; /* end o= ffset */ + return reg; +} + +static void aspeed_2700_smc_reg_to_segment(const AspeedSMCState *s, + uint32_t reg, AspeedSegments *s= eg) +{ + uint32_t start_offset =3D (reg << 16) & AST2700_SEG_ADDR_MASK; + uint32_t end_offset =3D reg & AST2700_SEG_ADDR_MASK; + AspeedSMCClass *asc =3D ASPEED_SMC_GET_CLASS(s); + + if (reg) { + seg->addr =3D asc->flash_window_base + start_offset; + seg->size =3D end_offset + (64 * KiB) - start_offset; + } else { + seg->addr =3D asc->flash_window_base; + seg->size =3D 0; + } +} + +static const uint32_t aspeed_2700_fmc_resets[ASPEED_SMC_R_MAX] =3D { + [R_CONF] =3D (CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE0 | + CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE1), + [R_CE_CTRL] =3D 0x0000aa00, + [R_CTRL0] =3D 0x406b0641, + [R_CTRL1] =3D 0x00000400, + [R_CTRL2] =3D 0x00000400, + [R_CTRL3] =3D 0x00000400, + [R_SEG_ADDR0] =3D 0x08000000, + [R_SEG_ADDR1] =3D 0x10000800, + [R_SEG_ADDR2] =3D 0x00000000, + [R_SEG_ADDR3] =3D 0x00000000, + [R_DUMMY_DATA] =3D 0x00010000, + [R_DMA_DRAM_ADDR_HIGH] =3D 0x00000000, + [R_TIMINGS] =3D 0x007b0000, +}; + +static const MemoryRegionOps aspeed_2700_smc_flash_ops =3D { + .read =3D aspeed_smc_flash_read, + .write =3D aspeed_smc_flash_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 8, + }, +}; + +static const AspeedSegments aspeed_2700_fmc_segments[] =3D { + { 0x0, 128 * MiB }, /* start address is readonly */ + { 128 * MiB, 128 * MiB }, /* default is disabled but needed for -kerne= l */ + { 256 * MiB, 128 * MiB }, /* default is disabled but needed for -kerne= l */ + { 0x0, 0 }, /* disabled */ +}; + +static void aspeed_2700_fmc_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + AspeedSMCClass *asc =3D ASPEED_SMC_CLASS(klass); + + dc->desc =3D "Aspeed 2700 FMC Controller"; + asc->r_conf =3D R_CONF; + asc->r_ce_ctrl =3D R_CE_CTRL; + asc->r_ctrl0 =3D R_CTRL0; + asc->r_timings =3D R_TIMINGS; + asc->nregs_timings =3D 3; + asc->conf_enable_w0 =3D CONF_ENABLE_W0; + asc->cs_num_max =3D 3; + asc->segments =3D aspeed_2700_fmc_segments; + asc->segment_addr_mask =3D 0xffffffff; + asc->resets =3D aspeed_2700_fmc_resets; + asc->flash_window_base =3D 0x100000000; + asc->flash_window_size =3D 1 * GiB; + asc->features =3D ASPEED_SMC_FEATURE_DMA | + ASPEED_SMC_FEATURE_DMA_DRAM_ADDR_HIGH; + asc->dma_flash_mask =3D 0x2FFFFFFC; + asc->dma_dram_mask =3D 0xFFFFFFFC; + asc->dma_start_length =3D 1; + asc->nregs =3D ASPEED_SMC_R_MAX; + asc->segment_to_reg =3D aspeed_2700_smc_segment_to_reg; + asc->reg_to_segment =3D aspeed_2700_smc_reg_to_segment; + asc->dma_ctrl =3D aspeed_2600_smc_dma_ctrl; + asc->reg_ops =3D &aspeed_2700_smc_flash_ops; +} + +static const TypeInfo aspeed_2700_fmc_info =3D { + .name =3D "aspeed.fmc-ast2700", + .parent =3D TYPE_ASPEED_SMC, + .class_init =3D aspeed_2700_fmc_class_init, +}; + +static const AspeedSegments aspeed_2700_spi0_segments[] =3D { + { 0x0, 128 * MiB }, /* start address is readonly */ + { 128 * MiB, 128 * MiB }, /* start address is readonly */ + { 0x0, 0 }, /* disabled */ +}; + +static void aspeed_2700_spi0_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + AspeedSMCClass *asc =3D ASPEED_SMC_CLASS(klass); + + dc->desc =3D "Aspeed 2700 SPI0 Controller"; + asc->r_conf =3D R_CONF; + asc->r_ce_ctrl =3D R_CE_CTRL; + asc->r_ctrl0 =3D R_CTRL0; + asc->r_timings =3D R_TIMINGS; + asc->nregs_timings =3D 2; + asc->conf_enable_w0 =3D CONF_ENABLE_W0; + asc->cs_num_max =3D 2; + asc->segments =3D aspeed_2700_spi0_segments; + asc->segment_addr_mask =3D 0xffffffff; + asc->flash_window_base =3D 0x180000000; + asc->flash_window_size =3D 1 * GiB; + asc->features =3D ASPEED_SMC_FEATURE_DMA | + ASPEED_SMC_FEATURE_DMA_DRAM_ADDR_HIGH; + asc->dma_flash_mask =3D 0x2FFFFFFC; + asc->dma_dram_mask =3D 0xFFFFFFFC; + asc->dma_start_length =3D 1; + asc->nregs =3D ASPEED_SMC_R_MAX; + asc->segment_to_reg =3D aspeed_2700_smc_segment_to_reg; + asc->reg_to_segment =3D aspeed_2700_smc_reg_to_segment; + asc->dma_ctrl =3D aspeed_2600_smc_dma_ctrl; + asc->reg_ops =3D &aspeed_2700_smc_flash_ops; +} + +static const TypeInfo aspeed_2700_spi0_info =3D { + .name =3D "aspeed.spi0-ast2700", + .parent =3D TYPE_ASPEED_SMC, + .class_init =3D aspeed_2700_spi0_class_init, +}; + +static const AspeedSegments aspeed_2700_spi1_segments[] =3D { + { 0x0, 128 * MiB }, /* start address is readonly */ + { 0x0, 0 }, /* disabled */ +}; + +static void aspeed_2700_spi1_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + AspeedSMCClass *asc =3D ASPEED_SMC_CLASS(klass); + + dc->desc =3D "Aspeed 2700 SPI1 Controller"; + asc->r_conf =3D R_CONF; + asc->r_ce_ctrl =3D R_CE_CTRL; + asc->r_ctrl0 =3D R_CTRL0; + asc->r_timings =3D R_TIMINGS; + asc->nregs_timings =3D 2; + asc->conf_enable_w0 =3D CONF_ENABLE_W0; + asc->cs_num_max =3D 2; + asc->segments =3D aspeed_2700_spi1_segments; + asc->segment_addr_mask =3D 0xffffffff; + asc->flash_window_base =3D 0x200000000; + asc->flash_window_size =3D 1 * GiB; + asc->features =3D ASPEED_SMC_FEATURE_DMA | + ASPEED_SMC_FEATURE_DMA_DRAM_ADDR_HIGH; + asc->dma_flash_mask =3D 0x2FFFFFFC; + asc->dma_dram_mask =3D 0xFFFFFFFC; + asc->dma_start_length =3D 1; + asc->nregs =3D ASPEED_SMC_R_MAX; + asc->segment_to_reg =3D aspeed_2700_smc_segment_to_reg; + asc->reg_to_segment =3D aspeed_2700_smc_reg_to_segment; + asc->dma_ctrl =3D aspeed_2600_smc_dma_ctrl; + asc->reg_ops =3D &aspeed_2700_smc_flash_ops; +} + +static const TypeInfo aspeed_2700_spi1_info =3D { + .name =3D "aspeed.spi1-ast2700", + .parent =3D TYPE_ASPEED_SMC, + .class_init =3D aspeed_2700_spi1_class_init, +}; + +static const AspeedSegments aspeed_2700_spi2_segments[] =3D { + { 0x0, 128 * MiB }, /* start address is readonly */ + { 0x0, 0 }, /* disabled */ +}; + +static void aspeed_2700_spi2_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + AspeedSMCClass *asc =3D ASPEED_SMC_CLASS(klass); + + dc->desc =3D "Aspeed 2700 SPI2 Controller"; + asc->r_conf =3D R_CONF; + asc->r_ce_ctrl =3D R_CE_CTRL; + asc->r_ctrl0 =3D R_CTRL0; + asc->r_timings =3D R_TIMINGS; + asc->nregs_timings =3D 2; + asc->conf_enable_w0 =3D CONF_ENABLE_W0; + asc->cs_num_max =3D 2; + asc->segments =3D aspeed_2700_spi2_segments; + asc->segment_addr_mask =3D 0xffffffff; + asc->flash_window_base =3D 0x280000000; + asc->flash_window_size =3D 1 * GiB; + asc->features =3D ASPEED_SMC_FEATURE_DMA | + ASPEED_SMC_FEATURE_DMA_DRAM_ADDR_HIGH; + asc->dma_flash_mask =3D 0x0FFFFFFC; + asc->dma_dram_mask =3D 0xFFFFFFFC; + asc->dma_start_length =3D 1; + asc->nregs =3D ASPEED_SMC_R_MAX; + asc->segment_to_reg =3D aspeed_2700_smc_segment_to_reg; + asc->reg_to_segment =3D aspeed_2700_smc_reg_to_segment; + asc->dma_ctrl =3D aspeed_2600_smc_dma_ctrl; + asc->reg_ops =3D &aspeed_2700_smc_flash_ops; +} + +static const TypeInfo aspeed_2700_spi2_info =3D { + .name =3D "aspeed.spi2-ast2700", + .parent =3D TYPE_ASPEED_SMC, + .class_init =3D aspeed_2700_spi2_class_init, +}; + static void aspeed_smc_register_types(void) { type_register_static(&aspeed_smc_flash_info); @@ -1954,6 +2182,10 @@ static void aspeed_smc_register_types(void) type_register_static(&aspeed_1030_fmc_info); type_register_static(&aspeed_1030_spi1_info); type_register_static(&aspeed_1030_spi2_info); + type_register_static(&aspeed_2700_fmc_info); + type_register_static(&aspeed_2700_spi0_info); + type_register_static(&aspeed_2700_spi1_info); + type_register_static(&aspeed_2700_spi2_info); } =20 type_init(aspeed_smc_register_types) --=20 2.45.2