From nobody Mon Nov 25 03:30:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1718322001; cv=none; d=zohomail.com; s=zohoarc; b=YRkk0vB33DsiczJ9D69wifPwoFE37vsyyU+MsLm2vDlgKhe51F05d/tGAZapgUF/upVBV9lMCTcClurf80pGNe5NI1uDI27xwTup2pDolQhkoYIFBURhdJf0bk+LUd4CrJKKcRORLzwRluAGSd0JowD+P0N/l+HvxdmU39ES66o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1718322001; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=KdCl/L0sNQIB0xy4r45UWawXnGaIeWIXwieKheQ81+8=; b=QTiIsYf7RbpVzjRNB4Y+9r/20LjkCBjv19/XLlNnYlFAC8PKI+yfR1D9Rn0xoATewH+moowM3XWz937+NFSAAoDr+YIwM2O0+rJ5HMKSDsOQIfWunO9NqCqlIkQiWmfj10Y8RWHEIMnkkoI1Edu/br6HU4USAeXDb5hBQNK1cBw= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1718322001251271.1495890165528; Thu, 13 Jun 2024 16:40:01 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sHu2i-0006QC-4Q; Thu, 13 Jun 2024 19:39:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sHu2T-0006Cn-Pf; Thu, 13 Jun 2024 19:39:30 -0400 Received: from frasgout.his.huawei.com ([185.176.79.56]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sHu2R-000341-5i; Thu, 13 Jun 2024 19:39:29 -0400 Received: from mail.maildlp.com (unknown [172.18.186.216]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4W0dzk4lrHz6HJ5h; Fri, 14 Jun 2024 07:34:42 +0800 (CST) Received: from lhrpeml500001.china.huawei.com (unknown [7.191.163.213]) by mail.maildlp.com (Postfix) with ESMTPS id F0C211400D9; Fri, 14 Jun 2024 07:39:24 +0800 (CST) Received: from 00293818-MRGF.china.huawei.com (10.195.245.24) by lhrpeml500001.china.huawei.com (7.191.163.213) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Fri, 14 Jun 2024 00:39:02 +0100 To: , , CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH RFC V3 04/29] hw/arm/virt: Move setting of common CPU properties in a function Date: Fri, 14 Jun 2024 00:36:14 +0100 Message-ID: <20240613233639.202896-5-salil.mehta@huawei.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240613233639.202896-1-salil.mehta@huawei.com> References: <20240613233639.202896-1-salil.mehta@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.195.245.24] X-ClientProxiedBy: dggems703-chm.china.huawei.com (10.3.19.180) To lhrpeml500001.china.huawei.com (7.191.163.213) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=salil.mehta@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Salil Mehta From: Salil Mehta via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1718322003071100003 Content-Type: text/plain; charset="utf-8" Factor out CPU properties code common for {hot,cold}-plugged CPUs. This all= ows code reuse. Signed-off-by: Salil Mehta --- hw/arm/virt.c | 261 ++++++++++++++++++++++++++++-------------- include/hw/arm/virt.h | 4 + 2 files changed, 182 insertions(+), 83 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 3e1c4d2d2f..2e0ec7d869 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1753,6 +1753,46 @@ static uint64_t virt_cpu_mp_affinity(VirtMachineStat= e *vms, int idx) return arm_build_mp_affinity(idx, clustersz); } =20 +static CPUArchId *virt_find_cpu_slot(MachineState *ms, int vcpuid) +{ + VirtMachineState *vms =3D VIRT_MACHINE(ms); + CPUArchId *found_cpu; + uint64_t mp_affinity; + + assert(vcpuid >=3D 0 && vcpuid < ms->possible_cpus->len); + + mp_affinity =3D virt_cpu_mp_affinity(vms, vcpuid); + found_cpu =3D &ms->possible_cpus->cpus[vcpuid]; + + assert(found_cpu->arch_id =3D=3D mp_affinity); + + /* + * RFC: Question: + * Slot-id is the index where vCPU with certain arch-id(=3Dmpidr/ap-af= finity) + * is plugged. For Host KVM, MPIDR for vCPU is derived using vcpu-id. + * As I understand, MPIDR and vcpu-id are property of vCPU but slot-id= is + * more related to machine? Current code assumes slot-id and vcpu-id a= re + * same i.e. meaning of slot is bit vague. + * + * Q1: Is there any requirement to clearly represent slot and dissocia= te it + * from vcpu-id? + * Q2: Should we make MPIDR within host KVM user configurable? + * + * +----+----+----+----+----+----+----+----+ + * MPIDR ||| Res | Aff2 | Aff1 | Aff0 | + * +----+----+----+----+----+----+----+----+ + * \ \ \ | | + * \ 8bit \ 8bit \ |4bit| + * \<------->\<------->\ |<-->| + * \ \ \| | + * +----+----+----+----+----+----+----+----+ + * VCPU-ID | Byte4 | Byte2 | Byte1 | Byte0 | + * +----+----+----+----+----+----+----+----+ + */ + + return found_cpu; +} + static inline bool *virt_get_high_memmap_enabled(VirtMachineState *vms, int index) { @@ -2065,16 +2105,129 @@ static void virt_cpu_post_init(VirtMachineState *v= ms, MemoryRegion *sysmem) } } =20 +static void virt_cpu_set_properties(Object *cpuobj, const CPUArchId *cpu_s= lot, + Error **errp) +{ + MachineState *ms =3D MACHINE(qdev_get_machine()); + VirtMachineState *vms =3D VIRT_MACHINE(ms); + Error *local_err =3D NULL; + VirtMachineClass *vmc; + + vmc =3D VIRT_MACHINE_GET_CLASS(ms); + + /* now, set the cpu object property values */ + numa_cpu_pre_plug(cpu_slot, DEVICE(cpuobj), &local_err); + if (local_err) { + goto out; + } + + object_property_set_int(cpuobj, "mp-affinity", cpu_slot->arch_id, NULL= ); + + if (!vms->secure) { + object_property_set_bool(cpuobj, "has_el3", false, NULL); + } + + if (!vms->virt && object_property_find(cpuobj, "has_el2")) { + object_property_set_bool(cpuobj, "has_el2", false, NULL); + } + + if (vmc->kvm_no_adjvtime && + object_property_find(cpuobj, "kvm-no-adjvtime")) { + object_property_set_bool(cpuobj, "kvm-no-adjvtime", true, NULL); + } + + if (vmc->no_kvm_steal_time && + object_property_find(cpuobj, "kvm-steal-time")) { + object_property_set_bool(cpuobj, "kvm-steal-time", false, NULL); + } + + if (vmc->no_pmu && object_property_find(cpuobj, "pmu")) { + object_property_set_bool(cpuobj, "pmu", false, NULL); + } + + if (vmc->no_tcg_lpa2 && object_property_find(cpuobj, "lpa2")) { + object_property_set_bool(cpuobj, "lpa2", false, NULL); + } + + if (object_property_find(cpuobj, "reset-cbar")) { + object_property_set_int(cpuobj, "reset-cbar", + vms->memmap[VIRT_CPUPERIPHS].base, + &local_err); + if (local_err) { + goto out; + } + } + + /* link already initialized {secure,tag}-memory regions to this cpu */ + object_property_set_link(cpuobj, "memory", OBJECT(vms->sysmem), &local= _err); + if (local_err) { + goto out; + } + + if (vms->secure) { + object_property_set_link(cpuobj, "secure-memory", + OBJECT(vms->secure_sysmem), &local_err); + if (local_err) { + goto out; + } + } + + if (vms->mte) { + if (!object_property_find(cpuobj, "tag-memory")) { + error_setg(&local_err, "MTE requested, but not supported " + "by the guest CPU"); + if (local_err) { + goto out; + } + } + + object_property_set_link(cpuobj, "tag-memory", OBJECT(vms->tag_sys= mem), + &local_err); + if (local_err) { + goto out; + } + + if (vms->secure) { + object_property_set_link(cpuobj, "secure-tag-memory", + OBJECT(vms->secure_tag_sysmem), + &local_err); + if (local_err) { + goto out; + } + } + } + + /* + * RFC: Question: this must only be called for the hotplugged cpus. Fo= r the + * cold booted secondary cpus this is being taken care in arm_load_ker= nel() + * in boot.c. Perhaps we should remove that code now? + */ + if (vms->psci_conduit !=3D QEMU_PSCI_CONDUIT_DISABLED) { + object_property_set_int(cpuobj, "psci-conduit", vms->psci_conduit, + NULL); + + /* Secondary CPUs start in PSCI powered-down state */ + if (CPU(cpuobj)->cpu_index > 0) { + object_property_set_bool(cpuobj, "start-powered-off", true, NU= LL); + } + } + +out: + if (local_err) { + error_propagate(errp, local_err); + } +} + static void machvirt_init(MachineState *machine) { VirtMachineState *vms =3D VIRT_MACHINE(machine); VirtMachineClass *vmc =3D VIRT_MACHINE_GET_CLASS(machine); MachineClass *mc =3D MACHINE_GET_CLASS(machine); const CPUArchIdList *possible_cpus; - MemoryRegion *sysmem =3D get_system_memory(); + MemoryRegion *secure_tag_sysmem =3D NULL; MemoryRegion *secure_sysmem =3D NULL; MemoryRegion *tag_sysmem =3D NULL; - MemoryRegion *secure_tag_sysmem =3D NULL; + MemoryRegion *sysmem; int n, virt_max_cpus; bool firmware_loaded; bool aarch64 =3D true; @@ -2148,6 +2301,8 @@ static void machvirt_init(MachineState *machine) /* uses smp.max_cpus to initialize all possible vCPUs */ possible_cpus =3D mc->possible_cpu_arch_ids(machine); =20 + sysmem =3D vms->sysmem =3D get_system_memory(); + if (vms->secure) { /* * The Secure view of the world is the same as the NonSecure, @@ -2155,7 +2310,7 @@ static void machvirt_init(MachineState *machine) * containing the system memory at low priority; any secure-only * devices go in at higher priority and take precedence. */ - secure_sysmem =3D g_new(MemoryRegion, 1); + secure_sysmem =3D vms->secure_sysmem =3D g_new(MemoryRegion, 1); memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory", UINT64_MAX); memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1); @@ -2203,10 +2358,28 @@ static void machvirt_init(MachineState *machine) exit(1); } =20 + if (vms->mte) { + /* Create the memory region only once, but link to all cpus later = */ + tag_sysmem =3D vms->tag_sysmem =3D g_new(MemoryRegion, 1); + memory_region_init(tag_sysmem, OBJECT(machine), + "tag-memory", UINT64_MAX / 32); + + if (vms->secure) { + secure_tag_sysmem =3D vms->secure_tag_sysmem =3D g_new(MemoryR= egion, 1); + memory_region_init(secure_tag_sysmem, OBJECT(machine), + "secure-tag-memory", UINT64_MAX / 32); + + /* As with ram, secure-tag takes precedence over tag. */ + memory_region_add_subregion_overlap(secure_tag_sysmem, 0, + tag_sysmem, -1); + } + } + create_fdt(vms); =20 assert(possible_cpus->len =3D=3D max_cpus); for (n =3D 0; n < possible_cpus->len; n++) { + CPUArchId *cpu_slot; Object *cpuobj; CPUState *cs; =20 @@ -2215,15 +2388,10 @@ static void machvirt_init(MachineState *machine) } =20 cpuobj =3D object_new(possible_cpus->cpus[n].type); - object_property_set_int(cpuobj, "mp-affinity", - possible_cpus->cpus[n].arch_id, NULL); =20 cs =3D CPU(cpuobj); cs->cpu_index =3D n; =20 - numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuo= bj), - &error_fatal); - aarch64 &=3D object_property_get_bool(cpuobj, "aarch64", NULL); object_property_set_int(cpuobj, "socket-id", virt_get_socket_id(machine, n), NULL); @@ -2234,81 +2402,8 @@ static void machvirt_init(MachineState *machine) object_property_set_int(cpuobj, "thread-id", virt_get_thread_id(machine, n), NULL); =20 - if (!vms->secure) { - object_property_set_bool(cpuobj, "has_el3", false, NULL); - } - - if (!vms->virt && object_property_find(cpuobj, "has_el2")) { - object_property_set_bool(cpuobj, "has_el2", false, NULL); - } - - if (vmc->kvm_no_adjvtime && - object_property_find(cpuobj, "kvm-no-adjvtime")) { - object_property_set_bool(cpuobj, "kvm-no-adjvtime", true, NULL= ); - } - - if (vmc->no_kvm_steal_time && - object_property_find(cpuobj, "kvm-steal-time")) { - object_property_set_bool(cpuobj, "kvm-steal-time", false, NULL= ); - } - - if (vmc->no_pmu && object_property_find(cpuobj, "pmu")) { - object_property_set_bool(cpuobj, "pmu", false, NULL); - } - - if (vmc->no_tcg_lpa2 && object_property_find(cpuobj, "lpa2")) { - object_property_set_bool(cpuobj, "lpa2", false, NULL); - } - - if (object_property_find(cpuobj, "reset-cbar")) { - object_property_set_int(cpuobj, "reset-cbar", - vms->memmap[VIRT_CPUPERIPHS].base, - &error_abort); - } - - object_property_set_link(cpuobj, "memory", OBJECT(sysmem), - &error_abort); - if (vms->secure) { - object_property_set_link(cpuobj, "secure-memory", - OBJECT(secure_sysmem), &error_abort); - } - - if (vms->mte) { - /* Create the memory region only once, but link to all cpus. */ - if (!tag_sysmem) { - /* - * The property exists only if MemTag is supported. - * If it is, we must allocate the ram to back that up. - */ - if (!object_property_find(cpuobj, "tag-memory")) { - error_report("MTE requested, but not supported " - "by the guest CPU"); - exit(1); - } - - tag_sysmem =3D g_new(MemoryRegion, 1); - memory_region_init(tag_sysmem, OBJECT(machine), - "tag-memory", UINT64_MAX / 32); - - if (vms->secure) { - secure_tag_sysmem =3D g_new(MemoryRegion, 1); - memory_region_init(secure_tag_sysmem, OBJECT(machine), - "secure-tag-memory", UINT64_MAX / 3= 2); - - /* As with ram, secure-tag takes precedence over tag. = */ - memory_region_add_subregion_overlap(secure_tag_sysmem,= 0, - tag_sysmem, -1); - } - } - - object_property_set_link(cpuobj, "tag-memory", OBJECT(tag_sysm= em), - &error_abort); - if (vms->secure) { - object_property_set_link(cpuobj, "secure-tag-memory", - OBJECT(secure_tag_sysmem), - &error_abort); - } - } + cpu_slot =3D virt_find_cpu_slot(machine, cs->cpu_index); + virt_cpu_set_properties(cpuobj, cpu_slot, &error_fatal); =20 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); object_unref(cpuobj); diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index 6f9a7bb60b..780bd53ceb 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -139,6 +139,10 @@ struct VirtMachineState { DeviceState *platform_bus_dev; FWCfgState *fw_cfg; PFlashCFI01 *flash[2]; + MemoryRegion *sysmem; + MemoryRegion *secure_sysmem; + MemoryRegion *tag_sysmem; + MemoryRegion *secure_tag_sysmem; bool secure; bool highmem; bool highmem_compact; --=20 2.34.1