From nobody Mon Nov 25 03:48:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1718321968; cv=none; d=zohomail.com; s=zohoarc; b=RUCyG70LHyCZ548Cj2VbkC9fEsA/p5YV/F7CVInE7yFGI0zxlzBRkgybLTpLlIy4CNo+mm97SeJeISPe7TSdaJtIBNXJsvO3vnrtGsikM0iQrErieipoCbauMdRTpWDFTv9wjQKggGLn01zxO2r+dcJ9Rbm/U7ooRMUksjqBvXg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1718321968; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=EUdUOzC0PfR6zZXK+5xJSDjjO6bpVpRmF/2NFeckt+8=; b=CxC/rQQ2SVuSqJ4UZwo8kwJGuSb7c1Mib+FSUDmM+jiiusc4TI5DgZGBaj97EBL81mMxSgAhLCKBmQ8XtdkpAM9sMyXLQ4wCGRW+ui2zLMQm9rsJLUlpzXooyRE+DzBJcKA5HdNlZRo2KcrdCU/QMnFaJFDOPsP6VFqFy5pq9s0= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1718321968794235.19303620883375; Thu, 13 Jun 2024 16:39:28 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sHu1T-00053x-JM; Thu, 13 Jun 2024 19:38:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sHu1R-00053Q-4Y; Thu, 13 Jun 2024 19:38:25 -0400 Received: from frasgout.his.huawei.com ([185.176.79.56]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sHu1P-0002y6-2S; Thu, 13 Jun 2024 19:38:24 -0400 Received: from mail.maildlp.com (unknown [172.18.186.31]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4W0f2F27fMz67kr9; Fri, 14 Jun 2024 07:36:53 +0800 (CST) Received: from lhrpeml500001.china.huawei.com (unknown [7.191.163.213]) by mail.maildlp.com (Postfix) with ESMTPS id B9FA7140594; Fri, 14 Jun 2024 07:38:16 +0800 (CST) Received: from 00293818-MRGF.china.huawei.com (10.195.245.24) by lhrpeml500001.china.huawei.com (7.191.163.213) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Fri, 14 Jun 2024 00:37:54 +0100 To: , , CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH RFC V3 01/29] arm/virt, target/arm: Add new ARMCPU {socket, cluster, core, thread}-id property Date: Fri, 14 Jun 2024 00:36:11 +0100 Message-ID: <20240613233639.202896-2-salil.mehta@huawei.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240613233639.202896-1-salil.mehta@huawei.com> References: <20240613233639.202896-1-salil.mehta@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.195.245.24] X-ClientProxiedBy: dggems703-chm.china.huawei.com (10.3.19.180) To lhrpeml500001.china.huawei.com (7.191.163.213) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=salil.mehta@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Salil Mehta From: Salil Mehta via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1718321970749100007 Content-Type: text/plain; charset="utf-8" This shall be used to store user specified topology{socket,cluster,core,thr= ead} and shall be converted to a unique 'vcpu-id' which is used as slot-index du= ring hot(un)plug of vCPU. Co-developed-by: Keqian Zhu Signed-off-by: Keqian Zhu Signed-off-by: Salil Mehta --- hw/arm/virt.c | 10 ++++++++++ include/hw/arm/virt.h | 28 ++++++++++++++++++++++++++++ target/arm/cpu.c | 4 ++++ target/arm/cpu.h | 4 ++++ 4 files changed, 46 insertions(+) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 3c93c0c0a6..11fc7fc318 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -2215,6 +2215,14 @@ static void machvirt_init(MachineState *machine) &error_fatal); =20 aarch64 &=3D object_property_get_bool(cpuobj, "aarch64", NULL); + object_property_set_int(cpuobj, "socket-id", + virt_get_socket_id(machine, n), NULL); + object_property_set_int(cpuobj, "cluster-id", + virt_get_cluster_id(machine, n), NULL); + object_property_set_int(cpuobj, "core-id", + virt_get_core_id(machine, n), NULL); + object_property_set_int(cpuobj, "thread-id", + virt_get_thread_id(machine, n), NULL); =20 if (!vms->secure) { object_property_set_bool(cpuobj, "has_el3", false, NULL); @@ -2708,6 +2716,7 @@ static const CPUArchIdList *virt_possible_cpu_arch_id= s(MachineState *ms) { int n; unsigned int max_cpus =3D ms->smp.max_cpus; + unsigned int smp_threads =3D ms->smp.threads; VirtMachineState *vms =3D VIRT_MACHINE(ms); MachineClass *mc =3D MACHINE_GET_CLASS(vms); =20 @@ -2721,6 +2730,7 @@ static const CPUArchIdList *virt_possible_cpu_arch_id= s(MachineState *ms) ms->possible_cpus->len =3D max_cpus; for (n =3D 0; n < ms->possible_cpus->len; n++) { ms->possible_cpus->cpus[n].type =3D ms->cpu_type; + ms->possible_cpus->cpus[n].vcpus_count =3D smp_threads; ms->possible_cpus->cpus[n].arch_id =3D virt_cpu_mp_affinity(vms, n); =20 diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index bb486d36b1..6f9a7bb60b 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -209,4 +209,32 @@ static inline int virt_gicv3_redist_region_count(VirtM= achineState *vms) vms->highmem_redists) ? 2 : 1; } =20 +static inline int virt_get_socket_id(const MachineState *ms, int cpu_index) +{ + assert(cpu_index >=3D 0 && cpu_index < ms->possible_cpus->len); + + return ms->possible_cpus->cpus[cpu_index].props.socket_id; +} + +static inline int virt_get_cluster_id(const MachineState *ms, int cpu_inde= x) +{ + assert(cpu_index >=3D 0 && cpu_index < ms->possible_cpus->len); + + return ms->possible_cpus->cpus[cpu_index].props.cluster_id; +} + +static inline int virt_get_core_id(const MachineState *ms, int cpu_index) +{ + assert(cpu_index >=3D 0 && cpu_index < ms->possible_cpus->len); + + return ms->possible_cpus->cpus[cpu_index].props.core_id; +} + +static inline int virt_get_thread_id(const MachineState *ms, int cpu_index) +{ + assert(cpu_index >=3D 0 && cpu_index < ms->possible_cpus->len); + + return ms->possible_cpus->cpus[cpu_index].props.thread_id; +} + #endif /* QEMU_ARM_VIRT_H */ diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 77f8c9c748..abc4ed0842 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2582,6 +2582,10 @@ static Property arm_cpu_properties[] =3D { DEFINE_PROP_UINT64("mp-affinity", ARMCPU, mp_affinity, ARM64_AFFINITY_INVALID), DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID), + DEFINE_PROP_INT32("socket-id", ARMCPU, socket_id, 0), + DEFINE_PROP_INT32("cluster-id", ARMCPU, cluster_id, 0), + DEFINE_PROP_INT32("core-id", ARMCPU, core_id, 0), + DEFINE_PROP_INT32("thread-id", ARMCPU, thread_id, 0), DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1), /* True to default to the backward-compat old CNTFRQ rather than 1Ghz = */ DEFINE_PROP_BOOL("backcompat-cntfrq", ARMCPU, backcompat_cntfrq, false= ), diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c17264c239..208c719db3 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1076,6 +1076,10 @@ struct ArchCPU { QLIST_HEAD(, ARMELChangeHook) el_change_hooks; =20 int32_t node_id; /* NUMA node this CPU belongs to */ + int32_t socket_id; + int32_t cluster_id; + int32_t core_id; + int32_t thread_id; =20 /* Used to synchronize KVM and QEMU in-kernel device levels */ uint8_t device_irq_level; --=20 2.34.1