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Signed-off-by: Sai Pavan Boddu --- hw/misc/zynq_slcr.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/hw/misc/zynq_slcr.c b/hw/misc/zynq_slcr.c index 3412ff099e..72703e92a5 100644 --- a/hw/misc/zynq_slcr.c +++ b/hw/misc/zynq_slcr.c @@ -24,6 +24,7 @@ #include "hw/registerfields.h" #include "hw/qdev-clock.h" #include "qom/object.h" +#include "hw/qdev-properties.h" =20 #ifndef ZYNQ_SLCR_ERR_DEBUG #define ZYNQ_SLCR_ERR_DEBUG 0 @@ -121,6 +122,7 @@ REG32(RST_REASON, 0x250) =20 REG32(REBOOT_STATUS, 0x258) REG32(BOOT_MODE, 0x25c) + FIELD(BOOT_MODE, BOOT_MODE, 0, 4) =20 REG32(APU_CTRL, 0x300) REG32(WDT_CLK_SEL, 0x304) @@ -195,6 +197,7 @@ struct ZynqSLCRState { Clock *ps_clk; Clock *uart0_ref_clk; Clock *uart1_ref_clk; + uint8_t BootMode; }; =20 /* @@ -371,7 +374,7 @@ static void zynq_slcr_reset_init(Object *obj, ResetType= type) s->regs[R_FPGA_RST_CTRL] =3D 0x01F33F0F; s->regs[R_RST_REASON] =3D 0x00000040; =20 - s->regs[R_BOOT_MODE] =3D 0x00000001; + s->regs[R_BOOT_MODE] =3D s->BootMode & R_BOOT_MODE_BOOT_MODE_MASK; =20 /* 0x700 - 0x7D4 */ for (i =3D 0; i < 54; i++) { @@ -610,6 +613,11 @@ static const VMStateDescription vmstate_zynq_slcr =3D { } }; =20 +static Property zynq_slcr_props[] =3D { + DEFINE_PROP_UINT8("boot-mode", ZynqSLCRState, BootMode, 1), + DEFINE_PROP_END_OF_LIST(), +}; + static void zynq_slcr_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); @@ -619,6 +627,7 @@ static void zynq_slcr_class_init(ObjectClass *klass, vo= id *data) rc->phases.enter =3D zynq_slcr_reset_init; rc->phases.hold =3D zynq_slcr_reset_hold; rc->phases.exit =3D zynq_slcr_reset_exit; + device_class_set_props(dc, zynq_slcr_props); } =20 static const TypeInfo zynq_slcr_info =3D { --=20 2.34.1 From nobody Mon Nov 25 01:30:58 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=amd.com); 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Signed-off-by: Sai Pavan Boddu --- hw/arm/xilinx_zynq.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index 7f7a3d23fb..4dfa9184ac 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -38,6 +38,7 @@ #include "qom/object.h" #include "exec/tswap.h" #include "target/arm/cpu-qom.h" +#include "qapi/visitor.h" =20 #define TYPE_ZYNQ_MACHINE MACHINE_TYPE_NAME("xilinx-zynq-a9") OBJECT_DECLARE_SIMPLE_TYPE(ZynqMachineState, ZYNQ_MACHINE) @@ -90,6 +91,7 @@ struct ZynqMachineState { MachineState parent; Clock *ps_clk; ARMCPU *cpu[ZYNQ_MAX_CPUS]; + uint8_t BootMode; }; =20 static void zynq_write_board_setup(ARMCPU *cpu, @@ -176,6 +178,19 @@ static inline int zynq_init_spi_flashes(uint32_t base_= addr, qemu_irq irq, return unit; } =20 +static void zynq_set_boot_mode(Object *obj, Visitor *v, + const char *name, void *opaque, + Error **errp) +{ + ZynqMachineState *m =3D ZYNQ_MACHINE(obj); + uint8_t val; + + if (!visit_type_uint8(v, name, &val, errp)) { + return; + } + m->BootMode =3D val; +} + static void zynq_init(MachineState *machine) { ZynqMachineState *zynq_machine =3D ZYNQ_MACHINE(machine); @@ -241,6 +256,7 @@ static void zynq_init(MachineState *machine) /* Create slcr, keep a pointer to connect clocks */ slcr =3D qdev_new("xilinx-zynq_slcr"); qdev_connect_clock_in(slcr, "ps_clk", zynq_machine->ps_clk); + qdev_prop_set_uint8(slcr, "boot-mode", zynq_machine->BootMode); sysbus_realize_and_unref(SYS_BUS_DEVICE(slcr), &error_fatal); sysbus_mmio_map(SYS_BUS_DEVICE(slcr), 0, 0xF8000000); =20 @@ -372,6 +388,7 @@ static void zynq_machine_class_init(ObjectClass *oc, vo= id *data) NULL }; MachineClass *mc =3D MACHINE_CLASS(oc); + ObjectProperty *prop; mc->desc =3D "Xilinx Zynq Platform Baseboard for Cortex-A9"; mc->init =3D zynq_init; mc->max_cpus =3D ZYNQ_MAX_CPUS; @@ -379,6 +396,11 @@ static void zynq_machine_class_init(ObjectClass *oc, v= oid *data) mc->ignore_memory_transaction_failures =3D true; mc->valid_cpu_types =3D valid_cpu_types; mc->default_ram_id =3D "zynq.ext_ram"; + prop =3D object_class_property_add(oc, "boot-mode", "uint8_t", NULL, + zynq_set_boot_mode, NULL, NULL); + object_class_property_set_description(oc, "boot-mode", + "Update SLCR.BOOT_MODE register"= ); + object_property_set_default_uint(prop, 1); } =20 static const TypeInfo zynq_machine_type =3D { --=20 2.34.1