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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f8393e8e53sm11363875ad.16.2024.06.12.01.15.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Jun 2024 01:15:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1718180140; x=1718784940; darn=nongnu.org; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=qTKcjK5EXlwx4nqxpoQ63FtP6DiDpTwQjxOyBCiDETw=; b=lFfMiJnuRSMxvcN3y146qLzn0zh54CU578qa5ae8Cti7/Ev38ZnO/UOGTa0if9+1pv AiPTEQtRksTFdwSXLV++uEw7r4m/po4RPXwb+tFPQYT5D4+dMloh59j2MaDmUte71I2e gDfgmAiflIF6itrDeN3qsK58iRp9a7JYnLuJKDwv2UugAsX+d6WoJRnQxvrrQX6wa8T7 udy/uJb+fk2hcfRqYeg0jrXOY22pxZJuYd66C2q/+5r6CdicpxOUpUdXHGs4eUtREumE FOVKYF5GhL76n0IkFtwwnrOpl7+m7p1i8/mFLHlsC20/P1CkUcOKPjDzxSneffo048Dc GgbQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1718180140; x=1718784940; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=qTKcjK5EXlwx4nqxpoQ63FtP6DiDpTwQjxOyBCiDETw=; b=f1fBrogoAt4j9ZFG1LlAC+wuzVLqRR0Lvw8m1/k1lAD6AemzvkPk+oIwy8Cp1+eF8O OVIRI+wdda/KMCS5Z31wDLg2oxcZ3dXftFeAuCBlj0kRlqSJjUnJxe1h/u/HD55Qq0SW 1eYCL+3CYLRp/PlAYQR9dPL00voFTYiBcXvk2FU7aG5Ps7dlEaH6OOSkZiRs8WoR9Idv Rc1EATXLU9x/McRVAiHH891BU4rZXgDmphu1MnZKUA76Lf9088nWOKR9aGwtcl9WOD6s Xr3lLlPJiEyiGdL6VId7L24Izu1qtLl4Sp7D+72n0LyIVtLyIywwCONmdMC2bjxRp2y1 xG/g== X-Gm-Message-State: AOJu0YylD9QNPx2HuQZJ6d7/CIrYvoigoMFVOKbYJwQ3MxG4yQ4wMEbk MNwjKoT85bVYZ/g891223Cl/QJT1mQfd2BjDLZHGGlTAVd1W/ytfqHXRzBzM2bZZRu7rob1WocX Or2qGUPxAPTuFO1ICZk3PI0yuS8gPRmBqYRJmDMQQCoScJ8ITJ+9bN6h7ZofAceqd4bZzpYjHr4 H1lG5uB3Ss2xHBRFkRp/BeUzonQJ9S3w2x3h8EY7zWug== X-Google-Smtp-Source: AGHT+IF/M2n8DqJvULKMMitCPhVPOFUwXB80CobMLfkGQhNAASkvBjBQM8JQ6otDp4pxad3wPRyQfg== X-Received: by 2002:a05:6a20:914c:b0:1b5:d063:3396 with SMTP id adf61e73a8af0-1b8a9c4e255mr1276925637.59.1718180139441; Wed, 12 Jun 2024 01:15:39 -0700 (PDT) From: Jim Shu To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Richard Henderson , Paolo Bonzini , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Eduardo Habkost , Marcel Apfelbaum , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , Peter Xu , David Hildenbrand , Peter Maydell , Michael Rolnik , "Edgar E. Iglesias" , Song Gao , Laurent Vivier , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo , Stafford Horne , Nicholas Piggin , Yoshinori Sato , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Bastian Koppelmann , Max Filippov , qemu-arm@nongnu.org (open list:ARM TCG CPUs), qemu-ppc@nongnu.org (open list:PowerPC TCG CPUs), qemu-s390x@nongnu.org (open list:S390 TCG CPUs), Jim Shu Subject: [RFC PATCH 11/16] hw/misc: riscv_worldguard: Add API to enable WG extension of CPU Date: Wed, 12 Jun 2024 16:14:11 +0800 Message-Id: <20240612081416.29704-12-jim.shu@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240612081416.29704-1-jim.shu@sifive.com> References: <20240612081416.29704-1-jim.shu@sifive.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=jim.shu@sifive.com; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1718180254859100005 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" riscv_worldguard_apply_cpu() could enable WG CPU extension and set WG callback to CPUs. It is used by machine code after realizing global WG device. Signed-off-by: Jim Shu --- hw/misc/riscv_worldguard.c | 87 ++++++++++++++++++++++++++++++ include/hw/misc/riscv_worldguard.h | 1 + 2 files changed, 88 insertions(+) diff --git a/hw/misc/riscv_worldguard.c b/hw/misc/riscv_worldguard.c index c839cc4e87..836ba43239 100644 --- a/hw/misc/riscv_worldguard.c +++ b/hw/misc/riscv_worldguard.c @@ -93,6 +93,93 @@ uint32_t mem_attrs_to_wid(MemTxAttrs attrs) } } =20 +static void riscv_cpu_wg_reset(CPURISCVState *env) +{ + CPUState *cs =3D env_cpu(env); + RISCVCPU *cpu =3D RISCV_CPU(cs); + uint32_t mlwid, slwid, mwiddeleg; + uint32_t trustedwid; + + if (!riscv_cpu_cfg(env)->ext_smwg) { + return; + } + + if (worldguard_config =3D=3D NULL) { + /* + * Note: This reset is dummy now and WG CSRs will be reset again + * after worldguard_config is realized. + */ + return; + } + + trustedwid =3D worldguard_config->trustedwid; + if (trustedwid =3D=3D NO_TRUSTEDWID) { + trustedwid =3D worldguard_config->nworlds - 1; + } + + /* Reset mlwid, slwid, mwiddeleg CSRs */ + if (worldguard_config->hw_bypass) { + /* HW bypass mode */ + mlwid =3D trustedwid; + } else { + mlwid =3D 0; + } + slwid =3D 0; + mwiddeleg =3D 0; + + env->mlwid =3D mlwid; + if (riscv_cpu_cfg(env)->ext_sswg) { + env->slwid =3D slwid; + env->mwiddeleg =3D mwiddeleg; + } + + /* Check mwid, mwidlist config */ + if (worldguard_config !=3D NULL) { + uint32_t valid_widlist =3D MAKE_64BIT_MASK(0, worldguard_config->n= worlds); + + /* CPU use default mwid / mwidlist config if not set */ + if (cpu->cfg.mwidlist =3D=3D UINT32_MAX) { + /* mwidlist contains all WIDs */ + cpu->cfg.mwidlist =3D valid_widlist; + } + if (cpu->cfg.mwid =3D=3D UINT32_MAX) { + cpu->cfg.mwid =3D trustedwid; + } + + /* Check if mwid/mwidlist HW config is valid in NWorld. */ + g_assert((cpu->cfg.mwidlist & ~valid_widlist) =3D=3D 0); + g_assert(cpu->cfg.mwid < worldguard_config->nworlds); + } +} + +/* + * riscv_worldguard_apply_cpu - Enable WG extension of CPU + * + * Note: This API should be used after global WG device is created + * (riscv_worldguard_realize()). + */ +void riscv_worldguard_apply_cpu(uint32_t hartid) +{ + /* WG global config should exist */ + g_assert(worldguard_config); + + CPUState *cpu =3D qemu_get_cpu(hartid); + RISCVCPU *rcpu =3D RISCV_CPU(cpu); + CPURISCVState *env =3D cpu ? cpu_env(cpu) : NULL; + + rcpu->cfg.ext_smwg =3D true; + if (riscv_has_ext(env, RVS) && riscv_has_ext(env, RVU)) { + rcpu->cfg.ext_sswg =3D true; + } + + /* Set machine specific WorldGuard callback */ + env->wg_reset =3D riscv_cpu_wg_reset; + env->wid_to_mem_attrs =3D wid_to_mem_attrs; + + /* Reset WG CSRs in CPU */ + env->wg_reset(env); +} + bool could_access_wgblocks(MemTxAttrs attrs, const char *wgblock) { uint32_t wid =3D mem_attrs_to_wid(attrs); diff --git a/include/hw/misc/riscv_worldguard.h b/include/hw/misc/riscv_wor= ldguard.h index 8a533a0517..211a72e438 100644 --- a/include/hw/misc/riscv_worldguard.h +++ b/include/hw/misc/riscv_worldguard.h @@ -48,6 +48,7 @@ extern struct RISCVWorldGuardState *worldguard_config; =20 DeviceState *riscv_worldguard_create(uint32_t nworlds, uint32_t trustedwid, bool hw_bypass, bool tz_compat); +void riscv_worldguard_apply_cpu(uint32_t hartid); =20 uint32_t mem_attrs_to_wid(MemTxAttrs attrs); bool could_access_wgblocks(MemTxAttrs attrs, const char *wgblock); --=20 2.17.1