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Sat, 08 Jun 2024 01:41:34 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHLQ+iKIHvNgnv55Yco+FipE5yyOJ/2Pz4LC+niCyi2r1u6X7QaSd0tbDEz7YxulKizGSQ9kg== X-Received: by 2002:a50:d7ca:0:b0:578:638e:3683 with SMTP id 4fb4d7f45d1cf-57c50861ae8mr3510740a12.5.1717836094394; Sat, 08 Jun 2024 01:41:34 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Subject: [PATCH 05/25] target/i386: change X86_ENTRYwr to use T0, use it for moves Date: Sat, 8 Jun 2024 10:40:53 +0200 Message-ID: <20240608084113.2770363-6-pbonzini@redhat.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240608084113.2770363-1-pbonzini@redhat.com> References: <20240608084113.2770363-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1717836248340100001 Content-Type: text/plain; charset="utf-8" Just like X86_ENTRYr, X86_ENTRYwr is easily changed to use only T0. In this case, the motivation is to use it for the MOV instruction family. The case when you need to preserve the input value is the odd one, as it is used basically only for BLS* instructions. Signed-off-by: Paolo Bonzini Reviewed-by: Richard Henderson --- target/i386/tcg/decode-new.c.inc | 48 ++++++++++++++++---------------- target/i386/tcg/emit.c.inc | 2 +- 2 files changed, 25 insertions(+), 25 deletions(-) diff --git a/target/i386/tcg/decode-new.c.inc b/target/i386/tcg/decode-new.= c.inc index f9d3e2577b2..d41002e2f5c 100644 --- a/target/i386/tcg/decode-new.c.inc +++ b/target/i386/tcg/decode-new.c.inc @@ -180,7 +180,7 @@ #define X86_OP_ENTRYrr(op, op0, s0, op1, s1, ...) \ X86_OP_ENTRY3(op, None, None, op0, s0, op1, s1, ## __VA_ARGS__) #define X86_OP_ENTRYwr(op, op0, s0, op1, s1, ...) \ - X86_OP_ENTRY3(op, op0, s0, None, None, op1, s1, ## __VA_ARGS__) + X86_OP_ENTRY3(op, op0, s0, op1, s1, None, None, ## __VA_ARGS__) #define X86_OP_ENTRY2(op, op0, s0, op1, s1, ...) \ X86_OP_ENTRY3(op, op0, s0, 2op, s0, op1, s1, ## __VA_ARGS__) #define X86_OP_ENTRYw(op, op0, s0, ...) \ @@ -612,15 +612,15 @@ static const X86OpEntry opcodes_0F38_00toEF[240] =3D { /* five rows for no prefix, 66, F3, F2, 66+F2 */ static const X86OpEntry opcodes_0F38_F0toFF[16][5] =3D { [0] =3D { - X86_OP_ENTRY3(MOVBE, G,y, M,y, None,None, cpuid(MOVBE)), - X86_OP_ENTRY3(MOVBE, G,w, M,w, None,None, cpuid(MOVBE)), + X86_OP_ENTRYwr(MOVBE, G,y, M,y, cpuid(MOVBE)), + X86_OP_ENTRYwr(MOVBE, G,w, M,w, cpuid(MOVBE)), {}, X86_OP_ENTRY2(CRC32, G,d, E,b, cpuid(SSE42)), X86_OP_ENTRY2(CRC32, G,d, E,b, cpuid(SSE42)), }, [1] =3D { - X86_OP_ENTRY3(MOVBE, M,y, G,y, None,None, cpuid(MOVBE)), - X86_OP_ENTRY3(MOVBE, M,w, G,w, None,None, cpuid(MOVBE)), + X86_OP_ENTRYwr(MOVBE, M,y, G,y, cpuid(MOVBE)), + X86_OP_ENTRYwr(MOVBE, M,w, G,w, cpuid(MOVBE)), {}, X86_OP_ENTRY2(CRC32, G,d, E,y, cpuid(SSE42)), X86_OP_ENTRY2(CRC32, G,d, E,w, cpuid(SSE42)), @@ -1586,18 +1586,18 @@ static const X86OpEntry opcodes_root[256] =3D { [0x7E] =3D X86_OP_ENTRYr(Jcc, J,b), [0x7F] =3D X86_OP_ENTRYr(Jcc, J,b), =20 - [0x88] =3D X86_OP_ENTRY3(MOV, E,b, G,b, None, None), - [0x89] =3D X86_OP_ENTRY3(MOV, E,v, G,v, None, None), - [0x8A] =3D X86_OP_ENTRY3(MOV, G,b, E,b, None, None), - [0x8B] =3D X86_OP_ENTRY3(MOV, G,v, E,v, None, None), - /* Missing in Table A-2: memory destination is always 16-bit. */ - [0x8C] =3D X86_OP_ENTRY3(MOV, E,v, S,w, None, None, op0_Mw), - [0x8D] =3D X86_OP_ENTRY3(LEA, G,v, M,v, None, None, noseg), - [0x8E] =3D X86_OP_ENTRY3(MOV, S,w, E,w, None, None), + [0x88] =3D X86_OP_ENTRYwr(MOV, E,b, G,b), + [0x89] =3D X86_OP_ENTRYwr(MOV, E,v, G,v), + [0x8A] =3D X86_OP_ENTRYwr(MOV, G,b, E,b), + [0x8B] =3D X86_OP_ENTRYwr(MOV, G,v, E,v), + /* Missing in Table A-2: memory destination is always 16-bit. */ + [0x8C] =3D X86_OP_ENTRYwr(MOV, E,v, S,w, op0_Mw), + [0x8D] =3D X86_OP_ENTRYwr(LEA, G,v, M,v, noseg), + [0x8E] =3D X86_OP_ENTRYwr(MOV, S,w, E,w), [0x8F] =3D X86_OP_GROUPw(group1A, E,v), =20 [0x98] =3D X86_OP_ENTRY1(CBW, 0,v), /* rAX */ - [0x99] =3D X86_OP_ENTRY3(CWD, 2,v, 0,v, None, None), /* rDX, rAX */ + [0x99] =3D X86_OP_ENTRYwr(CWD, 2,v, 0,v), /* rDX, rAX */ [0x9A] =3D X86_OP_ENTRYrr(CALLF, I_unsigned,p, I_unsigned,w, chk(i64)), [0x9B] =3D X86_OP_ENTRY0(WAIT), [0x9C] =3D X86_OP_ENTRY0(PUSHF, chk(vm86_iopl) svm(PUSHF)), @@ -1607,22 +1607,22 @@ static const X86OpEntry opcodes_root[256] =3D { =20 [0xA8] =3D X86_OP_ENTRYrr(AND, 0,b, I,b), /* AL, Ib */ [0xA9] =3D X86_OP_ENTRYrr(AND, 0,v, I,z), /* rAX, Iz */ - [0xAA] =3D X86_OP_ENTRY3(STOS, Y,b, 0,b, None, None), - [0xAB] =3D X86_OP_ENTRY3(STOS, Y,v, 0,v, None, None), + [0xAA] =3D X86_OP_ENTRYwr(STOS, Y,b, 0,b), + [0xAB] =3D X86_OP_ENTRYwr(STOS, Y,v, 0,v), /* Manual writeback because REP LODS (!) has to write EAX/RAX after ev= ery LODS. */ [0xAC] =3D X86_OP_ENTRYr(LODS, X,b), [0xAD] =3D X86_OP_ENTRYr(LODS, X,v), [0xAE] =3D X86_OP_ENTRYrr(SCAS, 0,b, Y,b), [0xAF] =3D X86_OP_ENTRYrr(SCAS, 0,v, Y,v), =20 - [0xB8] =3D X86_OP_ENTRY3(MOV, LoBits,v, I,v, None, None), - [0xB9] =3D X86_OP_ENTRY3(MOV, LoBits,v, I,v, None, None), - [0xBA] =3D X86_OP_ENTRY3(MOV, LoBits,v, I,v, None, None), - [0xBB] =3D X86_OP_ENTRY3(MOV, LoBits,v, I,v, None, None), - [0xBC] =3D X86_OP_ENTRY3(MOV, LoBits,v, I,v, None, None), - [0xBD] =3D X86_OP_ENTRY3(MOV, LoBits,v, I,v, None, None), - [0xBE] =3D X86_OP_ENTRY3(MOV, LoBits,v, I,v, None, None), - [0xBF] =3D X86_OP_ENTRY3(MOV, LoBits,v, I,v, None, None), + [0xB8] =3D X86_OP_ENTRYwr(MOV, LoBits,v, I,v), + [0xB9] =3D X86_OP_ENTRYwr(MOV, LoBits,v, I,v), + [0xBA] =3D X86_OP_ENTRYwr(MOV, LoBits,v, I,v), + [0xBB] =3D X86_OP_ENTRYwr(MOV, LoBits,v, I,v), + [0xBC] =3D X86_OP_ENTRYwr(MOV, LoBits,v, I,v), + [0xBD] =3D X86_OP_ENTRYwr(MOV, LoBits,v, I,v), + [0xBE] =3D X86_OP_ENTRYwr(MOV, LoBits,v, I,v), + [0xBF] =3D X86_OP_ENTRYwr(MOV, LoBits,v, I,v), =20 [0xC8] =3D X86_OP_ENTRYrr(ENTER, I,w, I,b), [0xC9] =3D X86_OP_ENTRY1(LEAVE, A,d64), diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc index 797e6e81406..78d89db57cd 100644 --- a/target/i386/tcg/emit.c.inc +++ b/target/i386/tcg/emit.c.inc @@ -1796,7 +1796,7 @@ static void gen_IN(DisasContext *s, X86DecodedInsn *d= ecode) MemOp ot =3D decode->op[0].ot; TCGv_i32 port =3D tcg_temp_new_i32(); =20 - tcg_gen_trunc_tl_i32(port, s->T1); + tcg_gen_trunc_tl_i32(port, s->T0); tcg_gen_ext16u_i32(port, port); if (!gen_check_io(s, ot, port, SVM_IOIO_TYPE_MASK)) { return; --=20 2.45.1