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Sat, 08 Jun 2024 01:41:31 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGOo9Fj/DJGoiKps1F1sFyEpY1f/8rp/5ACPDRLIVfaYCiOcYFJlaYI9wwSHhc8MoalsYMHdQ== X-Received: by 2002:a17:906:f58b:b0:a55:8f2a:950d with SMTP id a640c23a62f3a-a6cd56111d7mr379508866b.16.1717836090803; Sat, 08 Jun 2024 01:41:30 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Subject: [PATCH 04/25] target/i386: change X86_ENTRYr to use T0 Date: Sat, 8 Jun 2024 10:40:52 +0200 Message-ID: <20240608084113.2770363-5-pbonzini@redhat.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240608084113.2770363-1-pbonzini@redhat.com> References: <20240608084113.2770363-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1717836198216100003 Content-Type: text/plain; charset="utf-8" I am not sure why I made it use T1. It is a bit more symmetric with respect to X86_ENTRYwr (which uses T0 for the "w"ritten operand and T1 for the "r"ead operand), but it is also less flexible because it does not let you apply zextT0/sextT0. Signed-off-by: Paolo Bonzini Acked-by: Richard Henderson --- target/i386/tcg/decode-new.c.inc | 6 +++--- target/i386/tcg/emit.c.inc | 34 ++++++++++++++++---------------- 2 files changed, 20 insertions(+), 20 deletions(-) diff --git a/target/i386/tcg/decode-new.c.inc b/target/i386/tcg/decode-new.= c.inc index 380fb793531..f9d3e2577b2 100644 --- a/target/i386/tcg/decode-new.c.inc +++ b/target/i386/tcg/decode-new.c.inc @@ -186,7 +186,7 @@ #define X86_OP_ENTRYw(op, op0, s0, ...) \ X86_OP_ENTRY3(op, op0, s0, None, None, None, None, ## __VA_ARGS__) #define X86_OP_ENTRYr(op, op0, s0, ...) \ - X86_OP_ENTRY3(op, None, None, None, None, op0, s0, ## __VA_ARGS__) + X86_OP_ENTRY3(op, None, None, op0, s0, None, None, ## __VA_ARGS__) #define X86_OP_ENTRY1(op, op0, s0, ...) \ X86_OP_ENTRY3(op, op0, s0, 2op, s0, None, None, ## __VA_ARGS__) #define X86_OP_ENTRY0(op, ...) \ @@ -1335,9 +1335,9 @@ static void decode_group4_5(DisasContext *s, CPUX86St= ate *env, X86OpEntry *entry /* 0xff */ [0x08] =3D X86_OP_ENTRY1(INC, E,v, l= ock), [0x09] =3D X86_OP_ENTRY1(DEC, E,v, l= ock), - [0x0a] =3D X86_OP_ENTRY3(CALL_m, None, None, E,f64, None, None, z= extT0), + [0x0a] =3D X86_OP_ENTRYr(CALL_m, E,f64, z= extT0), [0x0b] =3D X86_OP_ENTRYr(CALLF_m, M,p), - [0x0c] =3D X86_OP_ENTRY3(JMP_m, None, None, E,f64, None, None, z= extT0), + [0x0c] =3D X86_OP_ENTRYr(JMP_m, E,f64, z= extT0), [0x0d] =3D X86_OP_ENTRYr(JMPF_m, M,p), [0x0e] =3D X86_OP_ENTRYr(PUSH, E,f64), }; diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc index a25b3dfc6b5..797e6e81406 100644 --- a/target/i386/tcg/emit.c.inc +++ b/target/i386/tcg/emit.c.inc @@ -1363,7 +1363,7 @@ static void gen_CALLF(DisasContext *s, X86DecodedInsn= *decode) =20 static void gen_CALLF_m(DisasContext *s, X86DecodedInsn *decode) { - MemOp ot =3D decode->op[2].ot; + MemOp ot =3D decode->op[1].ot; =20 gen_op_ld_v(s, ot, s->T0, s->A0); gen_add_A0_im(s, 1 << ot); @@ -1593,22 +1593,22 @@ static void gen_DEC(DisasContext *s, X86DecodedInsn= *decode) =20 static void gen_DIV(DisasContext *s, X86DecodedInsn *decode) { - MemOp ot =3D decode->op[2].ot; + MemOp ot =3D decode->op[1].ot; =20 switch(ot) { case MO_8: - gen_helper_divb_AL(tcg_env, s->T1); + gen_helper_divb_AL(tcg_env, s->T0); break; case MO_16: - gen_helper_divw_AX(tcg_env, s->T1); + gen_helper_divw_AX(tcg_env, s->T0); break; default: case MO_32: - gen_helper_divl_EAX(tcg_env, s->T1); + gen_helper_divl_EAX(tcg_env, s->T0); break; #ifdef TARGET_X86_64 case MO_64: - gen_helper_divq_EAX(tcg_env, s->T1); + gen_helper_divq_EAX(tcg_env, s->T0); break; #endif } @@ -1649,22 +1649,22 @@ static void gen_HLT(DisasContext *s, X86DecodedInsn= *decode) =20 static void gen_IDIV(DisasContext *s, X86DecodedInsn *decode) { - MemOp ot =3D decode->op[2].ot; + MemOp ot =3D decode->op[1].ot; =20 switch(ot) { case MO_8: - gen_helper_idivb_AL(tcg_env, s->T1); + gen_helper_idivb_AL(tcg_env, s->T0); break; case MO_16: - gen_helper_idivw_AX(tcg_env, s->T1); + gen_helper_idivw_AX(tcg_env, s->T0); break; default: case MO_32: - gen_helper_idivl_EAX(tcg_env, s->T1); + gen_helper_idivl_EAX(tcg_env, s->T0); break; #ifdef TARGET_X86_64 case MO_64: - gen_helper_idivq_EAX(tcg_env, s->T1); + gen_helper_idivq_EAX(tcg_env, s->T0); break; #endif } @@ -1926,7 +1926,7 @@ static void gen_JMPF(DisasContext *s, X86DecodedInsn = *decode) =20 static void gen_JMPF_m(DisasContext *s, X86DecodedInsn *decode) { - MemOp ot =3D decode->op[2].ot; + MemOp ot =3D decode->op[1].ot; =20 gen_op_ld_v(s, ot, s->T0, s->A0); gen_add_A0_im(s, 1 << ot); @@ -1947,7 +1947,7 @@ static void gen_LAHF(DisasContext *s, X86DecodedInsn = *decode) =20 static void gen_LDMXCSR(DisasContext *s, X86DecodedInsn *decode) { - tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T1); + tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0); gen_helper_ldmxcsr(tcg_env, s->tmp2_i32); } =20 @@ -1995,7 +1995,7 @@ static void gen_LGS(DisasContext *s, X86DecodedInsn *= decode) =20 static void gen_LODS(DisasContext *s, X86DecodedInsn *decode) { - MemOp ot =3D decode->op[2].ot; + MemOp ot =3D decode->op[1].ot; if (s->prefix & (PREFIX_REPZ | PREFIX_REPNZ)) { gen_repz(s, ot, gen_lods); } else { @@ -2765,7 +2765,7 @@ static void gen_PSLLDQ_i(DisasContext *s, X86DecodedI= nsn *decode) =20 static void gen_PUSH(DisasContext *s, X86DecodedInsn *decode) { - gen_push_v(s, s->T1); + gen_push_v(s, s->T0); } =20 static void gen_PUSHA(DisasContext *s, X86DecodedInsn *decode) @@ -3077,7 +3077,7 @@ static void gen_RCR(DisasContext *s, X86DecodedInsn *= decode) =20 static void gen_RET(DisasContext *s, X86DecodedInsn *decode) { - int16_t adjust =3D decode->e.op2 =3D=3D X86_TYPE_I ? decode->immediate= : 0; + int16_t adjust =3D decode->e.op1 =3D=3D X86_TYPE_I ? decode->immediate= : 0; =20 MemOp ot =3D gen_pop_T0(s); gen_stack_update(s, adjust + (1 << ot)); @@ -3088,7 +3088,7 @@ static void gen_RET(DisasContext *s, X86DecodedInsn *= decode) =20 static void gen_RETF(DisasContext *s, X86DecodedInsn *decode) { - int16_t adjust =3D decode->e.op2 =3D=3D X86_TYPE_I ? decode->immediate= : 0; + int16_t adjust =3D decode->e.op1 =3D=3D X86_TYPE_I ? decode->immediate= : 0; =20 if (!PE(s) || VM86(s)) { gen_lea_ss_ofs(s, s->A0, cpu_regs[R_ESP], 0); --=20 2.45.1