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Sat, 08 Jun 2024 01:41:27 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGHWeSRnnMPsCh19PhVvwzrWfzYSw6Ve4+4X9m8BQ16gZHV/W9jTQhnUsdb4CeciiN97SvL8A== X-Received: by 2002:a17:907:bb88:b0:a63:cd85:4d7b with SMTP id a640c23a62f3a-a6cdb00066fmr282582666b.62.1717836086838; Sat, 08 Jun 2024 01:41:26 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Subject: [PATCH 03/25] target/i386: put BLS* input in T1, use generic flag writeback Date: Sat, 8 Jun 2024 10:40:51 +0200 Message-ID: <20240608084113.2770363-4-pbonzini@redhat.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240608084113.2770363-1-pbonzini@redhat.com> References: <20240608084113.2770363-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1717836150109100003 Content-Type: text/plain; charset="utf-8" This makes for easier cpu_cc_* setup, and not using set_cc_op() should come in handy if QEMU ever implements APX. Signed-off-by: Paolo Bonzini Reviewed-by: Richard Henderson --- target/i386/tcg/decode-new.c.inc | 4 ++-- target/i386/tcg/emit.c.inc | 24 +++++++++--------------- 2 files changed, 11 insertions(+), 17 deletions(-) diff --git a/target/i386/tcg/decode-new.c.inc b/target/i386/tcg/decode-new.= c.inc index e7d88020481..380fb793531 100644 --- a/target/i386/tcg/decode-new.c.inc +++ b/target/i386/tcg/decode-new.c.inc @@ -633,7 +633,7 @@ static const X86OpEntry opcodes_0F38_F0toFF[16][5] =3D { {}, }, [3] =3D { - X86_OP_GROUP3(group17, B,y, E,y, None,None, vex13 cpuid(BMI1)), + X86_OP_GROUP3(group17, B,y, None,None, E,y, vex13 cpuid(BMI1)), {}, {}, {}, @@ -2604,7 +2604,7 @@ static void disas_insn(DisasContext *s, CPUState *cpu) } =20 /* - * Write back flags after last memory access. Some newer ALU instruct= ions, as + * Write back flags after last memory access. Some older ALU instruct= ions, as * well as SSE instructions, write flags in the gen_* function, but th= at can * cause incorrect tracking of CC_OP for instructions that write to bo= th memory * and flags. diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc index 2041ea9d04a..a25b3dfc6b5 100644 --- a/target/i386/tcg/emit.c.inc +++ b/target/i386/tcg/emit.c.inc @@ -1272,40 +1272,34 @@ static void gen_BEXTR(DisasContext *s, X86DecodedIn= sn *decode) prepare_update1_cc(decode, s, CC_OP_LOGICB + ot); } =20 -/* BLSI do not have memory operands and can use set_cc_op. */ static void gen_BLSI(DisasContext *s, X86DecodedInsn *decode) { MemOp ot =3D decode->op[0].ot; =20 - tcg_gen_mov_tl(cpu_cc_src, s->T0); - tcg_gen_neg_tl(s->T1, s->T0); + /* input in T1, which is ready for prepare_update2_cc */ + tcg_gen_neg_tl(s->T0, s->T1); tcg_gen_and_tl(s->T0, s->T0, s->T1); - tcg_gen_mov_tl(cpu_cc_dst, s->T0); - set_cc_op(s, CC_OP_BMILGB + ot); + prepare_update2_cc(decode, s, CC_OP_BMILGB + ot); } =20 -/* BLSMSK do not have memory operands and can use set_cc_op. */ static void gen_BLSMSK(DisasContext *s, X86DecodedInsn *decode) { MemOp ot =3D decode->op[0].ot; =20 - tcg_gen_mov_tl(cpu_cc_src, s->T0); - tcg_gen_subi_tl(s->T1, s->T0, 1); + /* input in T1, which is ready for prepare_update2_cc */ + tcg_gen_subi_tl(s->T0, s->T1, 1); tcg_gen_xor_tl(s->T0, s->T0, s->T1); - tcg_gen_mov_tl(cpu_cc_dst, s->T0); - set_cc_op(s, CC_OP_BMILGB + ot); + prepare_update2_cc(decode, s, CC_OP_BMILGB + ot); } =20 -/* BLSR do not have memory operands and can use set_cc_op. */ static void gen_BLSR(DisasContext *s, X86DecodedInsn *decode) { MemOp ot =3D decode->op[0].ot; =20 - tcg_gen_mov_tl(cpu_cc_src, s->T0); - tcg_gen_subi_tl(s->T1, s->T0, 1); + /* input in T1, which is ready for prepare_update2_cc */ + tcg_gen_subi_tl(s->T0, s->T1, 1); tcg_gen_and_tl(s->T0, s->T0, s->T1); - tcg_gen_mov_tl(cpu_cc_dst, s->T0); - set_cc_op(s, CC_OP_BMILGB + ot); + prepare_update2_cc(decode, s, CC_OP_BMILGB + ot); } =20 static void gen_BOUND(DisasContext *s, X86DecodedInsn *decode) --=20 2.45.1