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Sat, 08 Jun 2024 01:41:23 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHTp2rekmeKG0Q7LFZ5oRGO+gUbnu5OnxCzHuM1FmltYKTYw98BFVUHVjzFdS2Za8s7isC9iw== X-Received: by 2002:a50:9308:0:b0:57c:6ba4:3d89 with SMTP id 4fb4d7f45d1cf-57c6ba4400cmr720262a12.40.1717836082546; Sat, 08 Jun 2024 01:41:22 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Subject: [PATCH 02/25] target/i386: rewrite flags writeback for ADCX/ADOX Date: Sat, 8 Jun 2024 10:40:50 +0200 Message-ID: <20240608084113.2770363-3-pbonzini@redhat.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240608084113.2770363-1-pbonzini@redhat.com> References: <20240608084113.2770363-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1717836182212100009 Content-Type: text/plain; charset="utf-8" Avoid using set_cc_op() in preparation for implementing APX; treat CC_OP_EFLAGS similar to the case where we have the "opposite" cc_op (CC_OP_ADOX for ADCX and CC_OP_ADCX for ADOX), except the resulting cc_op is not CC_OP_ADCOX. This is written easily as two "if"s, whose conditions are both false for CC_OP_EFLAGS, both true for CC_OP_ADCOX, and one each true for CC_OP_ADCX/ADOX. The new logic also makes it easy to drop usage of tmp0. Signed-off-by: Paolo Bonzini Reviewed-by: Richard Henderson --- target/i386/cpu.h | 9 +++--- target/i386/tcg/emit.c.inc | 61 ++++++++++++++++++++++---------------- 2 files changed, 40 insertions(+), 30 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 8fe28b67e0f..ee873a0ed84 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1260,6 +1260,8 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWo= rd w, /* Use a clearer name for this. */ #define CPU_INTERRUPT_INIT CPU_INTERRUPT_RESET =20 +#define CC_OP_HAS_EFLAGS(op) ((op) >=3D CC_OP_EFLAGS && (op) <=3D CC_OP_AD= COX) + /* Instead of computing the condition codes after each x86 instruction, * QEMU just stores one operand (called CC_SRC), the result * (called CC_DST) and the type of operation (called CC_OP). When the @@ -1270,6 +1272,9 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWo= rd w, typedef enum { CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */ CC_OP_EFLAGS, /* all cc are explicitly computed, CC_SRC =3D flags */ + CC_OP_ADCX, /* CC_DST =3D C, CC_SRC =3D rest. */ + CC_OP_ADOX, /* CC_DST =3D O, CC_SRC =3D rest. */ + CC_OP_ADCOX, /* CC_DST =3D C, CC_SRC2 =3D O, CC_SRC =3D rest. */ =20 CC_OP_MULB, /* modify all flags, C, O =3D (CC_SRC !=3D 0) */ CC_OP_MULW, @@ -1326,10 +1331,6 @@ typedef enum { CC_OP_BMILGL, CC_OP_BMILGQ, =20 - CC_OP_ADCX, /* CC_DST =3D C, CC_SRC =3D rest. */ - CC_OP_ADOX, /* CC_DST =3D O, CC_SRC =3D rest. */ - CC_OP_ADCOX, /* CC_DST =3D C, CC_SRC2 =3D O, CC_SRC =3D rest. */ - CC_OP_CLR, /* Z set, all other flags clear. */ CC_OP_POPCNT, /* Z via CC_SRC, all other flags clear. */ =20 diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc index df7597c7e2f..2041ea9d04a 100644 --- a/target/i386/tcg/emit.c.inc +++ b/target/i386/tcg/emit.c.inc @@ -1122,24 +1122,41 @@ static void gen_ADC(DisasContext *s, X86DecodedInsn= *decode) prepare_update3_cc(decode, s, CC_OP_ADCB + ot, c_in); } =20 -/* ADCX/ADOX do not have memory operands and can use set_cc_op. */ -static void gen_ADCOX(DisasContext *s, MemOp ot, int cc_op) +static void gen_ADCOX(DisasContext *s, X86DecodedInsn *decode, int cc_op) { - int opposite_cc_op; + MemOp ot =3D decode->op[0].ot; TCGv carry_in =3D NULL; - TCGv carry_out =3D (cc_op =3D=3D CC_OP_ADCX ? cpu_cc_dst : cpu_cc_src2= ); + TCGv *carry_out =3D (cc_op =3D=3D CC_OP_ADCX ? &decode->cc_dst : &deco= de->cc_src2); TCGv zero; =20 - if (cc_op =3D=3D s->cc_op || s->cc_op =3D=3D CC_OP_ADCOX) { - /* Re-use the carry-out from a previous round. */ - carry_in =3D carry_out; - } else { - /* We don't have a carry-in, get it out of EFLAGS. */ - if (s->cc_op !=3D CC_OP_ADCX && s->cc_op !=3D CC_OP_ADOX) { - gen_compute_eflags(s); + decode->cc_op =3D cc_op; + *carry_out =3D tcg_temp_new(); + if (CC_OP_HAS_EFLAGS(s->cc_op)) { + decode->cc_src =3D cpu_cc_src; + + /* Re-use the carry-out from a previous round? */ + if (s->cc_op =3D=3D cc_op || s->cc_op =3D=3D CC_OP_ADCOX) { + carry_in =3D (cc_op =3D=3D CC_OP_ADCX ? cpu_cc_dst : cpu_cc_sr= c2); } - carry_in =3D s->tmp0; - tcg_gen_extract_tl(carry_in, cpu_cc_src, + + /* Preserve the opposite carry from previous rounds? */ + if (s->cc_op !=3D cc_op && s->cc_op !=3D CC_OP_EFLAGS) { + decode->cc_op =3D CC_OP_ADCOX; + if (carry_out =3D=3D &decode->cc_dst) { + decode->cc_src2 =3D cpu_cc_src2; + } else { + decode->cc_dst =3D cpu_cc_dst; + } + } + } else { + decode->cc_src =3D tcg_temp_new(); + gen_mov_eflags(s, decode->cc_src); + } + + if (!carry_in) { + /* Get carry_in out of EFLAGS. */ + carry_in =3D tcg_temp_new(); + tcg_gen_extract_tl(carry_in, decode->cc_src, ctz32(cc_op =3D=3D CC_OP_ADCX ? CC_C : CC_O), 1); } =20 @@ -1151,28 +1168,20 @@ static void gen_ADCOX(DisasContext *s, MemOp ot, in= t cc_op) tcg_gen_ext32u_tl(s->T1, s->T1); tcg_gen_add_i64(s->T0, s->T0, s->T1); tcg_gen_add_i64(s->T0, s->T0, carry_in); - tcg_gen_shri_i64(carry_out, s->T0, 32); + tcg_gen_shri_i64(*carry_out, s->T0, 32); break; #endif default: zero =3D tcg_constant_tl(0); - tcg_gen_add2_tl(s->T0, carry_out, s->T0, zero, carry_in, zero); - tcg_gen_add2_tl(s->T0, carry_out, s->T0, carry_out, s->T1, zero); + tcg_gen_add2_tl(s->T0, *carry_out, s->T0, zero, carry_in, zero); + tcg_gen_add2_tl(s->T0, *carry_out, s->T0, *carry_out, s->T1, zero); break; } - - opposite_cc_op =3D cc_op =3D=3D CC_OP_ADCX ? CC_OP_ADOX : CC_OP_ADCX; - if (s->cc_op =3D=3D CC_OP_ADCOX || s->cc_op =3D=3D opposite_cc_op) { - /* Merge with the carry-out from the opposite instruction. */ - set_cc_op(s, CC_OP_ADCOX); - } else { - set_cc_op(s, cc_op); - } } =20 static void gen_ADCX(DisasContext *s, X86DecodedInsn *decode) { - gen_ADCOX(s, decode->op[0].ot, CC_OP_ADCX); + gen_ADCOX(s, decode, CC_OP_ADCX); } =20 static void gen_ADD(DisasContext *s, X86DecodedInsn *decode) @@ -1190,7 +1199,7 @@ static void gen_ADD(DisasContext *s, X86DecodedInsn *= decode) =20 static void gen_ADOX(DisasContext *s, X86DecodedInsn *decode) { - gen_ADCOX(s, decode->op[0].ot, CC_OP_ADOX); + gen_ADCOX(s, decode, CC_OP_ADOX); } =20 static void gen_AND(DisasContext *s, X86DecodedInsn *decode) --=20 2.45.1