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Sat, 08 Jun 2024 01:42:15 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFb8qM+V5BVgSKQuqQfuyfV/Lv3ZSadlaP06qzp+/h/dBVXWbOZm477wS+bk21U32rGdewWMQ== X-Received: by 2002:a17:906:3285:b0:a68:2f99:a3da with SMTP id a640c23a62f3a-a6cd5612575mr297920766b.16.1717836135122; Sat, 08 Jun 2024 01:42:15 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Subject: [PATCH 17/25] target/i386: convert SHLD/SHRD to new decoder Date: Sat, 8 Jun 2024 10:41:05 +0200 Message-ID: <20240608084113.2770363-18-pbonzini@redhat.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240608084113.2770363-1-pbonzini@redhat.com> References: <20240608084113.2770363-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1717836254403100007 Content-Type: text/plain; charset="utf-8" Use the same flag generation code as SHL and SHR, but use the existing gen_shiftd_rm_T1 function to compute the result as well as CC_SRC. Decoding-wise, SHLD/SHRD by immediate count as a 4 operand instruction because s->T0 and s->T1 actually occupy three op slots. The infrastructure used by opcodes in the 0F 3A table works fine. Signed-off-by: Paolo Bonzini Reviewed-by: Richard Henderson --- target/i386/tcg/translate.c | 83 +------------------------------- target/i386/tcg/decode-new.c.inc | 6 ++- target/i386/tcg/emit.c.inc | 42 ++++++++++++++++ 3 files changed, 48 insertions(+), 83 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 416db2f3b0e..1e9036eb6e3 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -1429,57 +1429,11 @@ static bool check_cpl0(DisasContext *s) return false; } =20 -static void gen_shift_flags(DisasContext *s, MemOp ot, TCGv result, - TCGv shm1, TCGv count, bool is_right) -{ - TCGv_i32 z32, s32, oldop; - TCGv z_tl; - - /* Store the results into the CC variables. If we know that the - variable must be dead, store unconditionally. Otherwise we'll - need to not disrupt the current contents. */ - z_tl =3D tcg_constant_tl(0); - if (cc_op_live[s->cc_op] & USES_CC_DST) { - tcg_gen_movcond_tl(TCG_COND_NE, cpu_cc_dst, count, z_tl, - result, cpu_cc_dst); - } else { - tcg_gen_mov_tl(cpu_cc_dst, result); - } - if (cc_op_live[s->cc_op] & USES_CC_SRC) { - tcg_gen_movcond_tl(TCG_COND_NE, cpu_cc_src, count, z_tl, - shm1, cpu_cc_src); - } else { - tcg_gen_mov_tl(cpu_cc_src, shm1); - } - - /* Get the two potential CC_OP values into temporaries. */ - tcg_gen_movi_i32(s->tmp2_i32, (is_right ? CC_OP_SARB : CC_OP_SHLB) + o= t); - if (s->cc_op =3D=3D CC_OP_DYNAMIC) { - oldop =3D cpu_cc_op; - } else { - tcg_gen_movi_i32(s->tmp3_i32, s->cc_op); - oldop =3D s->tmp3_i32; - } - - /* Conditionally store the CC_OP value. */ - z32 =3D tcg_constant_i32(0); - s32 =3D tcg_temp_new_i32(); - tcg_gen_trunc_tl_i32(s32, count); - tcg_gen_movcond_i32(TCG_COND_NE, cpu_cc_op, s32, z32, s->tmp2_i32, old= op); - - /* The CC_OP value is no longer predictable. */ - set_cc_op(s, CC_OP_DYNAMIC); -} - /* XXX: add faster immediate case */ -static TCGv gen_shiftd_rm_T1(DisasContext *s, MemOp ot, - bool is_right, TCGv count_in) +static void gen_shiftd_rm_T1(DisasContext *s, MemOp ot, + bool is_right, TCGv count) { target_ulong mask =3D (ot =3D=3D MO_64 ? 63 : 31); - TCGv count; - - count =3D tcg_temp_new(); - tcg_gen_andi_tl(count, count_in, mask); =20 switch (ot) { case MO_16: @@ -1541,8 +1495,6 @@ static TCGv gen_shiftd_rm_T1(DisasContext *s, MemOp o= t, tcg_gen_or_tl(s->T0, s->T0, s->T1); break; } - - return count; } =20 #define X86_MAX_INSN_LENGTH 15 @@ -3052,7 +3004,6 @@ static void disas_insn_old(DisasContext *s, CPUState = *cpu, int b) CPUX86State *env =3D cpu_env(cpu); int prefixes =3D s->prefix; MemOp dflag =3D s->dflag; - TCGv shift; MemOp ot; int modrm, reg, rm, mod, op; =20 @@ -3216,36 +3167,6 @@ static void disas_insn_old(DisasContext *s, CPUState= *cpu, int b) } break; =20 - /**************************/ - /* shifts */ - case 0x1a4: /* shld imm */ - op =3D 0; - shift =3D NULL; - goto do_shiftd; - case 0x1a5: /* shld cl */ - op =3D 0; - shift =3D cpu_regs[R_ECX]; - goto do_shiftd; - case 0x1ac: /* shrd imm */ - op =3D 1; - shift =3D NULL; - goto do_shiftd; - case 0x1ad: /* shrd cl */ - op =3D 1; - shift =3D cpu_regs[R_ECX]; - do_shiftd: - ot =3D dflag; - modrm =3D x86_ldub_code(env, s); - reg =3D ((modrm >> 3) & 7) | REX_R(s); - gen_ld_modrm(env, s, modrm, ot); - if (!shift) { - shift =3D tcg_constant_tl(x86_ldub_code(env, s)); - } - gen_op_mov_v_reg(s, ot, s->T1, reg); - shift =3D gen_shiftd_rm_T1(s, ot, op, shift); - gen_st_modrm(env, s, modrm, ot); - gen_shift_flags(s, ot, s->T0, s->tmp0, shift, op); - break; case 0x1bc: /* bsf / tzcnt */ case 0x1bd: /* bsr / lzcnt */ ot =3D dflag; diff --git a/target/i386/tcg/decode-new.c.inc b/target/i386/tcg/decode-new.= c.inc index af142d6911a..bd9e7cd4df9 100644 --- a/target/i386/tcg/decode-new.c.inc +++ b/target/i386/tcg/decode-new.c.inc @@ -1134,6 +1134,8 @@ static const X86OpEntry opcodes_0F[256] =3D { [0xa1] =3D X86_OP_ENTRYw(POP, FS, w), [0xa2] =3D X86_OP_ENTRY0(CPUID), [0xa3] =3D X86_OP_ENTRYrr(BT, E,v, G,v, btEvGv), + [0xa4] =3D X86_OP_ENTRY4(SHLD, E,v, 2op,v, G,v), + [0xa5] =3D X86_OP_ENTRY3(SHLD, E,v, 2op,v, G,v), =20 [0xb2] =3D X86_OP_ENTRY3(LSS, G,v, EM,p, None, None), [0xb3] =3D X86_OP_ENTRY2(BTR, E,v, G,v, btEvGv), @@ -1262,6 +1264,8 @@ static const X86OpEntry opcodes_0F[256] =3D { [0xa9] =3D X86_OP_ENTRYw(POP, GS, w), [0xaa] =3D X86_OP_ENTRY0(RSM, chk(smm) svm(RSM)), [0xab] =3D X86_OP_ENTRY2(BTS, E,v, G,v, btEvGv), + [0xac] =3D X86_OP_ENTRY4(SHRD, E,v, 2op,v, G,v), + [0xad] =3D X86_OP_ENTRY3(SHRD, E,v, 2op,v, G,v), [0xae] =3D X86_OP_GROUP0(group15), /* * It's slightly more efficient to put Ev operand in T0 and allow gen_= IMUL3 @@ -2557,8 +2561,6 @@ static void disas_insn(DisasContext *s, CPUState *cpu) switch (b) { case 0x00 ... 0x01: /* mostly privileged instructions */ case 0x1a ... 0x1b: /* MPX */ - case 0xa4 ... 0xa5: /* SHLD */ - case 0xac ... 0xad: /* SHRD */ case 0xb0 ... 0xb1: /* cmpxchg */ case 0xb8: /* POPCNT */ case 0xbc ... 0xbd: /* LZCNT/TZCNT */ diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc index 2e73b41cd3e..aabc86669c2 100644 --- a/target/i386/tcg/emit.c.inc +++ b/target/i386/tcg/emit.c.inc @@ -3708,6 +3708,27 @@ static void gen_SHL(DisasContext *s, X86DecodedInsn = *decode) } } =20 +static void gen_SHLD(DisasContext *s, X86DecodedInsn *decode) +{ + bool can_be_zero; + TCGv count; + int unit =3D decode->e.op3 =3D=3D X86_TYPE_I ? X86_OP_IMM : X86_OP_INT; + MemOp ot =3D gen_shift_count(s, decode, &can_be_zero, &count, unit); + + if (!count) { + return; + } + + decode->cc_dst =3D s->T0; + decode->cc_src =3D s->tmp0; + gen_shiftd_rm_T1(s, ot, false, count); + if (can_be_zero) { + gen_shift_dynamic_flags(s, decode, count, CC_OP_SHLB + ot); + } else { + decode->cc_op =3D CC_OP_SHLB + ot; + } +} + static void gen_SHLX(DisasContext *s, X86DecodedInsn *decode) { MemOp ot =3D decode->op[0].ot; @@ -3740,6 +3761,27 @@ static void gen_SHR(DisasContext *s, X86DecodedInsn = *decode) } } =20 +static void gen_SHRD(DisasContext *s, X86DecodedInsn *decode) +{ + bool can_be_zero; + TCGv count; + int unit =3D decode->e.op3 =3D=3D X86_TYPE_I ? X86_OP_IMM : X86_OP_INT; + MemOp ot =3D gen_shift_count(s, decode, &can_be_zero, &count, unit); + + if (!count) { + return; + } + + decode->cc_dst =3D s->T0; + decode->cc_src =3D s->tmp0; + gen_shiftd_rm_T1(s, ot, true, count); + if (can_be_zero) { + gen_shift_dynamic_flags(s, decode, count, CC_OP_SARB + ot); + } else { + decode->cc_op =3D CC_OP_SARB + ot; + } +} + static void gen_SHRX(DisasContext *s, X86DecodedInsn *decode) { MemOp ot =3D decode->op[0].ot; --=20 2.45.1