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Sat, 08 Jun 2024 01:42:09 -0700 (PDT) X-Google-Smtp-Source: AGHT+IG84wibuR6pFAitspADx3et4dNex5WEK3nOdESsZCnSIZWhzYRDua5Xuc+GARVjWEaZowtYZQ== X-Received: by 2002:a17:906:b313:b0:a6e:2a67:789f with SMTP id a640c23a62f3a-a6e2a677a24mr215073466b.40.1717836128611; Sat, 08 Jun 2024 01:42:08 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Subject: [PATCH 15/25] target/i386: pull load/writeback out of gen_shiftd_rm_T1 Date: Sat, 8 Jun 2024 10:41:03 +0200 Message-ID: <20240608084113.2770363-16-pbonzini@redhat.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240608084113.2770363-1-pbonzini@redhat.com> References: <20240608084113.2770363-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1717836208256100006 Content-Type: text/plain; charset="utf-8" Use gen_ld_modrm/gen_st_modrm, moving them and gen_shift_flags to the caller. This way, gen_shiftd_rm_T1 becomes something that the new decoder can call. Signed-off-by: Paolo Bonzini Reviewed-by: Richard Henderson --- target/i386/tcg/translate.c | 55 ++++++++++--------------------------- 1 file changed, 14 insertions(+), 41 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index c3843092350..416db2f3b0e 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -535,15 +535,6 @@ static inline void gen_op_st_v(DisasContext *s, int id= x, TCGv t0, TCGv a0) tcg_gen_qemu_st_tl(t0, a0, s->mem_index, idx | MO_LE); } =20 -static inline void gen_op_st_rm_T0_A0(DisasContext *s, int idx, int d) -{ - if (d =3D=3D OR_TMP0) { - gen_op_st_v(s, idx, s->T0, s->A0); - } else { - gen_op_mov_reg_v(s, idx, d, s->T0); - } -} - static void gen_update_eip_next(DisasContext *s) { assert(s->pc_save !=3D -1); @@ -1481,19 +1472,12 @@ static void gen_shift_flags(DisasContext *s, MemOp = ot, TCGv result, } =20 /* XXX: add faster immediate case */ -static void gen_shiftd_rm_T1(DisasContext *s, MemOp ot, int op1, +static TCGv gen_shiftd_rm_T1(DisasContext *s, MemOp ot, bool is_right, TCGv count_in) { target_ulong mask =3D (ot =3D=3D MO_64 ? 63 : 31); TCGv count; =20 - /* load */ - if (op1 =3D=3D OR_TMP0) { - gen_op_ld_v(s, ot, s->T0, s->A0); - } else { - gen_op_mov_v_reg(s, ot, s->T0, op1); - } - count =3D tcg_temp_new(); tcg_gen_andi_tl(count, count_in, mask); =20 @@ -1558,10 +1542,7 @@ static void gen_shiftd_rm_T1(DisasContext *s, MemOp = ot, int op1, break; } =20 - /* store */ - gen_op_st_rm_T0_A0(s, ot, op1); - - gen_shift_flags(s, ot, s->T0, s->tmp0, count, is_right); + return count; } =20 #define X86_MAX_INSN_LENGTH 15 @@ -3071,9 +3052,9 @@ static void disas_insn_old(DisasContext *s, CPUState = *cpu, int b) CPUX86State *env =3D cpu_env(cpu); int prefixes =3D s->prefix; MemOp dflag =3D s->dflag; - int shift; + TCGv shift; MemOp ot; - int modrm, reg, rm, mod, op, opreg; + int modrm, reg, rm, mod, op; =20 /* now check op code */ switch (b) { @@ -3239,39 +3220,31 @@ static void disas_insn_old(DisasContext *s, CPUStat= e *cpu, int b) /* shifts */ case 0x1a4: /* shld imm */ op =3D 0; - shift =3D 1; + shift =3D NULL; goto do_shiftd; case 0x1a5: /* shld cl */ op =3D 0; - shift =3D 0; + shift =3D cpu_regs[R_ECX]; goto do_shiftd; case 0x1ac: /* shrd imm */ op =3D 1; - shift =3D 1; + shift =3D NULL; goto do_shiftd; case 0x1ad: /* shrd cl */ op =3D 1; - shift =3D 0; + shift =3D cpu_regs[R_ECX]; do_shiftd: ot =3D dflag; modrm =3D x86_ldub_code(env, s); - mod =3D (modrm >> 6) & 3; - rm =3D (modrm & 7) | REX_B(s); reg =3D ((modrm >> 3) & 7) | REX_R(s); - if (mod !=3D 3) { - gen_lea_modrm(env, s, modrm); - opreg =3D OR_TMP0; - } else { - opreg =3D rm; + gen_ld_modrm(env, s, modrm, ot); + if (!shift) { + shift =3D tcg_constant_tl(x86_ldub_code(env, s)); } gen_op_mov_v_reg(s, ot, s->T1, reg); - - if (shift) { - TCGv imm =3D tcg_constant_tl(x86_ldub_code(env, s)); - gen_shiftd_rm_T1(s, ot, opreg, op, imm); - } else { - gen_shiftd_rm_T1(s, ot, opreg, op, cpu_regs[R_ECX]); - } + shift =3D gen_shiftd_rm_T1(s, ot, op, shift); + gen_st_modrm(env, s, modrm, ot); + gen_shift_flags(s, ot, s->T0, s->tmp0, shift, op); break; case 0x1bc: /* bsf / tzcnt */ case 0x1bd: /* bsr / lzcnt */ --=20 2.45.1