From nobody Mon Nov 25 04:51:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1717761667; cv=none; d=zohomail.com; s=zohoarc; b=CO+I6zsqSWaW3wu4wcN3OZUgcOvmxuS/Ppmn7X+6ZMosHRABaddt0VIJ7EJTd1Z4rh/EjqbQN/kzbTCMG1529jJwR23Ts/qbYmJyWSrhNUQrohhfLZ7QVjzz8u1/Ofp4SAXEdpY/CZmNLdnlcLum+a3hiV+tIK0sBQvVTns644o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1717761667; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=tALMS3Jb+5EphxGlSm8+jjwAHKeOcILEHP7gOqamHoo=; b=lFLv1TC7FFQ7qTSF8TXkKPI+dFQnLB6wX+yMG/Y21IQclua8vCSgLhVJzMqHJX+d23k8uUwgJrbWlsdE3orjCSJJ1+gnOeOgq7MiFPygqKqc5eVRWZf3Yc1pjN9uDrg44hroc7zgYiUbVGEwgu+uq3dCxdvvrqO2hlguHySVl0Y= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 17177616679041013.1716179027973; Fri, 7 Jun 2024 05:01:07 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sFYGw-0006Ii-Fw; Fri, 07 Jun 2024 08:00:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sFYG5-0005X3-35; Fri, 07 Jun 2024 07:59:51 -0400 Received: from frasgout.his.huawei.com ([185.176.79.56]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sFYG3-0000kW-07; Fri, 07 Jun 2024 07:59:48 -0400 Received: from mail.maildlp.com (unknown [172.18.186.31]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4VwflS5rb7z6HJqd; Fri, 7 Jun 2024 19:55:16 +0800 (CST) Received: from lhrpeml500001.china.huawei.com (unknown [7.191.163.213]) by mail.maildlp.com (Postfix) with ESMTPS id C0410140B2F; Fri, 7 Jun 2024 19:59:40 +0800 (CST) Received: from 00293818-MRGF.china.huawei.com (10.48.147.102) by lhrpeml500001.china.huawei.com (7.191.163.213) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Fri, 7 Jun 2024 12:59:17 +0100 To: , CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Jonathan Cameron , Shaoqin Huang , Zhao Liu Subject: [PATCH V13 5/8] hw/acpi: Update CPUs AML with cpu-(ctrl)dev change Date: Fri, 7 Jun 2024 12:56:46 +0100 Message-ID: <20240607115649.214622-6-salil.mehta@huawei.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240607115649.214622-1-salil.mehta@huawei.com> References: <20240607115649.214622-1-salil.mehta@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.48.147.102] X-ClientProxiedBy: dggems705-chm.china.huawei.com (10.3.19.182) To lhrpeml500001.china.huawei.com (7.191.163.213) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=salil.mehta@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Salil Mehta From: Salil Mehta via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1717761669877100003 Content-Type: text/plain; charset="utf-8" CPUs Control device(\\_SB.PCI0) register interface for the x86 arch is IO p= ort based and existing CPUs AML code assumes _CRS objects would evaluate to a s= ystem resource which describes IO Port address. But on ARM arch CPUs control device(\\_SB.PRES) register interface is memory-mapped hence _CRS object sh= ould evaluate to system resource which describes memory-mapped base address. Upd= ate build CPUs AML function to accept both IO/MEMORY region spaces and accordin= gly update the _CRS object. On x86, CPU Hotplug uses Generic ACPI GPE Block Bit 2 (GPE.2) event handler= to notify OSPM about any CPU hot(un)plug events. Latest CPU Hotplug is based on ACPI Generic Event Device framework and uses ACPI GED device for the same. = Not all architectures support GPE based CPU Hotplug event handler. Hence, make = AML for GPE.2 event handler conditional. Co-developed-by: Keqian Zhu Signed-off-by: Keqian Zhu Signed-off-by: Salil Mehta Reviewed-by: Gavin Shan Tested-by: Vishnu Pajjuri Reviewed-by: Jonathan Cameron Tested-by: Xianglai Li Tested-by: Miguel Luis Reviewed-by: Shaoqin Huang Tested-by: Zhao Liu --- hw/acpi/cpu.c | 23 ++++++++++++++++------- hw/i386/acpi-build.c | 3 ++- include/hw/acpi/cpu.h | 5 +++-- 3 files changed, 21 insertions(+), 10 deletions(-) diff --git a/hw/acpi/cpu.c b/hw/acpi/cpu.c index af2b6655d2..4c63514b16 100644 --- a/hw/acpi/cpu.c +++ b/hw/acpi/cpu.c @@ -343,9 +343,10 @@ const VMStateDescription vmstate_cpu_hotplug =3D { #define CPU_FW_EJECT_EVENT "CEJF" =20 void build_cpus_aml(Aml *table, MachineState *machine, CPUHotplugFeatures = opts, - build_madt_cpu_fn build_madt_cpu, hwaddr io_base, + build_madt_cpu_fn build_madt_cpu, hwaddr base_addr, const char *res_root, - const char *event_handler_method) + const char *event_handler_method, + AmlRegionSpace rs) { Aml *ifctx; Aml *field; @@ -370,13 +371,19 @@ void build_cpus_aml(Aml *table, MachineState *machine= , CPUHotplugFeatures opts, aml_append(cpu_ctrl_dev, aml_mutex(CPU_LOCK, 0)); =20 crs =3D aml_resource_template(); - aml_append(crs, aml_io(AML_DECODE16, io_base, io_base, 1, + if (rs =3D=3D AML_SYSTEM_IO) { + aml_append(crs, aml_io(AML_DECODE16, base_addr, base_addr, 1, ACPI_CPU_HOTPLUG_REG_LEN)); + } else { + aml_append(crs, aml_memory32_fixed(base_addr, + ACPI_CPU_HOTPLUG_REG_LEN, AML_READ_WRITE)); + } + aml_append(cpu_ctrl_dev, aml_name_decl("_CRS", crs)); =20 /* declare CPU hotplug MMIO region with related access fields */ aml_append(cpu_ctrl_dev, - aml_operation_region("PRST", AML_SYSTEM_IO, aml_int(io_base), + aml_operation_region("PRST", rs, aml_int(base_addr), ACPI_CPU_HOTPLUG_REG_LEN)); =20 field =3D aml_field("PRST", AML_BYTE_ACC, AML_NOLOCK, @@ -700,9 +707,11 @@ void build_cpus_aml(Aml *table, MachineState *machine,= CPUHotplugFeatures opts, aml_append(sb_scope, cpus_dev); aml_append(table, sb_scope); =20 - method =3D aml_method(event_handler_method, 0, AML_NOTSERIALIZED); - aml_append(method, aml_call0("\\_SB.CPUS." CPU_SCAN_METHOD)); - aml_append(table, method); + if (event_handler_method) { + method =3D aml_method(event_handler_method, 0, AML_NOTSERIALIZED); + aml_append(method, aml_call0("\\_SB.CPUS." CPU_SCAN_METHOD)); + aml_append(table, method); + } =20 g_free(cphp_res_path); } diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 53f804ac16..b73b136605 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -1537,7 +1537,8 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, .fw_unplugs_cpu =3D pm->smi_on_cpu_unplug, }; build_cpus_aml(dsdt, machine, opts, pc_madt_cpu_entry, - pm->cpu_hp_io_base, "\\_SB.PCI0", "\\_GPE._E02"); + pm->cpu_hp_io_base, "\\_SB.PCI0", "\\_GPE._E02", + AML_SYSTEM_IO); } =20 if (pcms->memhp_io_base && nr_mem) { diff --git a/include/hw/acpi/cpu.h b/include/hw/acpi/cpu.h index e6e1a9ef59..48cded697c 100644 --- a/include/hw/acpi/cpu.h +++ b/include/hw/acpi/cpu.h @@ -61,9 +61,10 @@ typedef void (*build_madt_cpu_fn)(int uid, const CPUArch= IdList *apic_ids, GArray *entry, bool force_enabled); =20 void build_cpus_aml(Aml *table, MachineState *machine, CPUHotplugFeatures = opts, - build_madt_cpu_fn build_madt_cpu, hwaddr io_base, + build_madt_cpu_fn build_madt_cpu, hwaddr base_addr, const char *res_root, - const char *event_handler_method); + const char *event_handler_method, + AmlRegionSpace rs); =20 void acpi_cpu_ospm_status(CPUHotplugState *cpu_st, ACPIOSTInfoList ***list= ); =20 --=20 2.34.1