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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-703fd50bc86sm1150919b3a.175.2024.06.06.06.49.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Jun 2024 06:49:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1717681793; x=1718286593; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=cEG1fPkJ+g/jXimIp5Gy6n7CLs83yHdB825jkzDzPOg=; b=ahTAZAZ8Vsy1cibU2EqGF9r9grVd1frTGBu2oHtowTum6mjrBpkRs/6FbzgjQQ4DiF jFSfF0I3aufsEVE3V/+bvtnzTi5rQkArWezH8SXMot0tTYVtjGD8pQPRD51zkW3hfs3K TAHqlQZBH0PGsVF8X867P4y1nGCvZhq7KsRhA+sKCbp2XtHmrsJ20LNq3edBRR37+djp vGNtimVtfF9jELL12xBvR6ztTVJM3MSVkja+/PV7V/OQS+y73jHfkr+AWJI6DwxfRKur R174Ov6DFYDGqcG2bflexDOGTkJgtd0CLzKLP+0b7IIrXDuqaxk5NXTQ5wWNlPwvRAH9 MG/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1717681793; x=1718286593; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=cEG1fPkJ+g/jXimIp5Gy6n7CLs83yHdB825jkzDzPOg=; b=ptIIquJknF+mj6uvfGyZ+714eY/doe2KEHDIAcMdjg66uhsaXeJ2+HnqKKE2aM3rh6 oeFNUGPr9AWGfjAJEQtCl3SU5DWZYRikKFDwzopiYo0VUUk+ZY8wcEGOGOq1D2WnMLOu kfL8Xc23NECXHkzFZAaCYN6OMMp7FJbldT23JwP9gecxSyIPHpBFwVp8aTm8P5RG/1+b JZ2SKGv0fYuELTfE5mr+kRknhj8lQv37OhFxjlsGIRib/riZzVptqIWeTwpVnyO0fZnS gePs5X1w9M1mtOgrMM7bFuWoaAlL46UeygtwIUoIOP2JSLK5iPqhJifRVLHlY+QLv91w 4PjQ== X-Gm-Message-State: AOJu0Yz0yfpDpzZWiwD7l01SvAdQYMUxyChn6x0W3g2t/DQMJYiqV1/u c52cWhqkSPhwGc4z5w/0p0d2/nsfo9pTHT9+26RvNLhrNPZUDof4gesl1V+cHY9/bPTN559pghv 6GyomntdI5StG18WnAM61Q4otSOxpM26Js/EkFp9j0uabPINexffKJPJRz7N6PuPK5KLhW6FJVG RmqAmh2hlr5Y2Kv2tvs9yKcBL40/pQcyPvYrs= X-Google-Smtp-Source: AGHT+IHdKISYxbIDFt7eqi9B3TUfLTHowMV9NWWnXgAGoNuJH6r/6Pn0q/CLElQptWDdrCUqcIbEcQ== X-Received: by 2002:a05:6a20:8423:b0:1a9:d9bb:acdc with SMTP id adf61e73a8af0-1b2b6ff70bfmr6534936637.28.1717681792576; Thu, 06 Jun 2024 06:49:52 -0700 (PDT) From: "Fea.Wang" To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , "Fea.Wang" , Frank Chang Subject: [PATCH v4 4/6] target/riscv: Add MEDELEGH, HEDELEGH csrs for RV32 Date: Thu, 6 Jun 2024 21:54:52 +0800 Message-Id: <20240606135454.119186-5-fea.wang@sifive.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240606135454.119186-1-fea.wang@sifive.com> References: <20240606135454.119186-1-fea.wang@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=fea.wang@sifive.com; helo=mail-pf1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1717681854768100002 Content-Type: text/plain; charset="utf-8" Based on privileged spec 1.13, the RV32 needs to implement MEDELEGH and HEDELEGH for exception codes 32-47 for reserving and exception codes 48-63 for custom use. Add the CSR number though the implementation is just reading zero and writing ignore. Besides, for accessing HEDELEGH, it should be controlled by mstateen0 'P1P13' bit. Signed-off-by: Fea.Wang Reviewed-by: Frank Chang Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis --- target/riscv/cpu_bits.h | 2 ++ target/riscv/csr.c | 31 +++++++++++++++++++++++++++++++ 2 files changed, 33 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index c895aa0334..096a51b331 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -156,6 +156,8 @@ =20 /* 32-bit only */ #define CSR_MSTATUSH 0x310 +#define CSR_MEDELEGH 0x312 +#define CSR_HEDELEGH 0x612 =20 /* Machine Trap Handling */ #define CSR_MSCRATCH 0x340 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index a19e1afa1f..6f15612e76 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -3229,6 +3229,33 @@ static RISCVException write_hedeleg(CPURISCVState *e= nv, int csrno, return RISCV_EXCP_NONE; } =20 +static RISCVException read_hedelegh(CPURISCVState *env, int csrno, + target_ulong *val) +{ + RISCVException ret; + ret =3D smstateen_acc_ok(env, 0, SMSTATEEN0_P1P13); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + + /* Reserved, now read zero */ + *val =3D 0; + return RISCV_EXCP_NONE; +} + +static RISCVException write_hedelegh(CPURISCVState *env, int csrno, + target_ulong val) +{ + RISCVException ret; + ret =3D smstateen_acc_ok(env, 0, SMSTATEEN0_P1P13); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + + /* Reserved, now write ignore */ + return RISCV_EXCP_NONE; +} + static RISCVException rmw_hvien64(CPURISCVState *env, int csrno, uint64_t *ret_val, uint64_t new_val, uint64_t wr_mask) @@ -4633,6 +4660,10 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { =20 [CSR_MSTATUSH] =3D { "mstatush", any32, read_mstatush, write_mstatush = }, + [CSR_MEDELEGH] =3D { "medelegh", any32, read_zero, write_ignore, + .min_priv_ver =3D PRIV_VERSION_1_13_0 = }, + [CSR_HEDELEGH] =3D { "hedelegh", hmode32, read_hedelegh, write_he= delegh, + .min_priv_ver =3D PRIV_VERSION_1_13_0 = }, =20 /* Machine Trap Handling */ [CSR_MSCRATCH] =3D { "mscratch", any, read_mscratch, write_mscratch, --=20 2.34.1